參數(shù)資料
型號: MC68HC05C0FN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 82/96頁
文件大?。?/td> 357K
代理商: MC68HC05C0FN
MOTOROLA
Section 12: Serial Communications Interface
Page 74
MC68HC05C0 Specification Rev. 1.2
12.6.3
SERIAL COMMUNICATIONS CONTROL REGISTER 2 (SCCR2)
The SCI Control Register 2 (SCCR2) provides control bits which individually enable/disable
the transmitter or receiver, enable the system interrupts, provide the wake-up enable bit,
and provide a "send break code" bit. All bits are read/writable. The flags are described in
Figure 12-11: Serial Communications Control Register 2
TIE- Transmit Interrupt Enable
1= TDRE interrupt enabled
0= TDRE interrupt disabled
TCIE - Transmit Complete Interrupt Enable
1= TC interrupt enabled
0 = TC interrupt disabled
RIE - Receiver Interrupt Enable
1= RDRF or OR (with RDRF) interrupt is enabled
0= RDRF and OR (with RDRF) interrupts disabled
ILIE - Idle Line Interrupt Enable
1= Idle interrupt disabled
0= Idle interrupt disabled
TE- Transmit Enable
When the transmit enable bit is set, the transmit shift register output is applied to the TDO
line and the corresponding clocks are applied to the SCK pin. Depending on the state of
control bit M (SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is
transmitted when software sets the TE bit from a cleared state.
If a transmission is in progress, and TE is written to a zero, then the transmitter will wait
until after the present byte has been transmitted before releasing the TDO and SCK (if
enabled) pins to their Data Direction Register control.
If the TE bit has been cleared and then set before the current byte has been transmitted,
the transmitter will wait until that byte is transmitted and will then initiate transmission of a
new preamble. After the preamble, the line will then be idle (high) or begin transmitting the
next byte if new data has been loaded.
RD
WR
RST
76543210
SCCR2
$16
0
SBK
RWU
RE
TIE
TCIE
RIE
ILIE
TE
0
000
0
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