Table of Contents
Figure
Number
Figure 4-19.16-Bit EEPROM Addressing.......................................................................4-51
Figure 4-20.8-Bit EEPROM Addressing.........................................................................4-51
Figure 4-21.Mixed Address EEPROM Addressing ........................................................4-52
Title
Page
Number
xiii
MC68SC302 USER’S MANUAL
MOTOROLA
Section 5
ISA Plug and Play Interface
Figure 5-1. SC302 Memory Spaces and Decoding Methods.........................................5-2
Figure 5-2. HCR Access in ISA Mode............................................................................5-3
Figure 5-3. CCMR Addressing in ISA I/O Space ...........................................................5-3
Figure 5-4. DPR Addressing..........................................................................................5-5
Figure 5-5. ISA-PNP Resource Data Layout in a Byte Serial EEPROM Device.............5-9
Figure 5-6. Internal I/O Space Structure......................................................................5-11
Figure 5-7. PNP - ISA Interconnection..........................................................................5-38
Figure 5-8. The LFSR Key Sequence...........................................................................5-38
Figure 5-9. Shifting of Serial Identifier...........................................................................5-39
Figure 5-10.Isolation State Transitions ..........................................................................5-41
Section 6
PCMCIA Interface
Figure 6-1. Parallel EPROM Configuration.....................................................................6-2
Figure 6-2. Serial EEPROM Configuration......................................................................6-2
Figure 6-3. 68SC302 PCMCIA Address Map in Serial CIS EEPROM Mode..................6-4
Figure 6-4. 68SC302 PCMCIA Address Map in Parallel CIS PROM Mode....................6-5
Figure 6-5. DPR Addressing...........................................................................................6-6
Figure 6-6. RI to STSCHG Path....................................................................................6-11
Section 7
Electrical Characteristics
Figure 7-1. CLKOUT Timing Specifications....................................................................7-4
Figure 7-2. CLKOUT Timing for CDIV 1-0=00 in CLKCNT............................................7-5
Figure 7-3. CLKOUT Timing for CDIV 1-0=10 in CLKCNT............................................7-5
Figure 7-4. CLKOUT Timing for CDIV 1-0=01 in CLKCNT............................................7-5
Figure 7-5. ISA Reset Timing Specifications..................................................................7-6
Figure 7-6. IO Space Read Access without Wait States for PnP and Internal Space.....7-8
Figure 7-7. IO Space Read Access without Wait States (PnP and Internal Space) -
the Special Case of Coupled Accesses........................................................7-9
Figure 7-8. IO Space Read Access without Wait States (Internal Space)....................7-10
Figure 7-9. IO Space Read Access without Wait States (Internal Space) -
the Special Case of Coupled Read Accesses............................................7-11
Figure 7-10. IO Space Read Access with Wait States...................................................7-12
Figure 7-11. IO Space Write Access without Wait states (PnP and Internal Space)....7-14
Figure 7-12. IO Space Write Access with Wait States - Internal Space.........................7-15
Figure 7-13. Memory Space Read Access without Wait States.....................................7-17
Figure 7-14.Memory Space Read Access with Wait States...........................................7-18
Figure 7-15.Memory Space Write Access without Wait States......................................7-20
Figure 7-16.Memory Space Write Access with Wait States...........................................7-21