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參數(shù)資料
| 型號(hào)： | MC68SC302 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁(yè)數(shù)： | 83/218頁(yè) |
| 文件大?。?/td> | 521K |
| 代理商： | MC68SC302 |
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Communications Processor (CP)
MOTOROLA
MC68SC302 USER’S MANUAL
4-37
data from memory and start transmitting the buffer. Transmission will not begin until the
internal transmit FIFO is preloaded and the SCC achieves synchronization if using the SI.
When a BD's data is completely transmitted, the last bit (L) is checked in the BD. If the L bit
is cleared, then the transmitter moves immediately to the next buffer to begin its
transmission, with no gap on the serial line between buffers. Failure to provide the next
buffer in time results in a transmit underrun, causing the TXE bit in the transparent event
register to be set.
If the L bit is set, the frame ends, and the transmission of ones resumes until a new buffer
is made ready. The next buffer will not begin transmission until achieving synchronization if
using the SI.
The transmit buffer length and starting address may be even or odd; however, since the
transparent transmitter reads a word at a time, better performance can be achieved with an
even buffer length and starting address. For example, if a transmit buffer begins on an odd-
byte boundary and is 10 bytes in length (the worst case), six word reads will result, even
though only 10 bytes will be transmitted.
Any whole number of bytes may be transmitted. If the REVD bit in the transparent mode
register is set, each data byte will be reversed in its bit order before transmission.
If the interrupt (I) bit in the TxBD is set, then the TX bit will be set in the transparent event
register following the transmission of the buffer. The TX bit can generate a maskable
interrupt.
4.5.11.2 TRANSPARENT CHANNEL BUFFER RECEPTION PROCESSING.
When the
host enables the transparent receiver, it will enter hunt mode. In this mode, if using the SI,
it waits to achieve synchronization before receiving data.
Once data reception begins, the transparent receiver begins moving data from the receive
FIFO to the receive buffer, always moving a 16-bit word at a time. The transparent receiver
continues to move data to the receive buffer until the buffer is completely full, as defined by
the byte count in MRBLR. The receive buffer length (stored in MRBLR) and starting address
must always be even, so the minimum receive buffer length must be 2.
After a buffer is filled, the transparent receiver moves to the next RxBD in the table and
begins moving data to its associated buffer.
If there is no place in the memory chunk for a new word, a busy condition is signified by the
setting of the BSY bit in the transparent event register, which can generate a maskable
interrupt.
Received data is always packed into memory a word at a time, regardless of how it is
received. For example, in NMSI mode, the first word of data will not be moved to the receive
buffer until after the sixteenth receive clock occurs.
Once synchronization is achieved for the receiver, the reception process continues
unabated until a busy condition occurs or a receive overrun occurs. The busy condition error
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| MC68SEC000AA10 | 功能描述:微處理器 - MPU 8/16/32 BIT MPU STATIC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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