參數(shù)資料
型號: MC68SC302
廠商: Motorola, Inc.
英文描述: 32-Bit Microprocessor(32位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁數(shù): 75/218頁
文件大?。?/td> 521K
代理商: MC68SC302
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Communications Processor (CP)
MOTOROLA
MC68SC302 USER’S MANUAL
4-29
mode, an interrupt is issued according to the interrupt bit in the BD. The HDLC controller will
then proceed to the next BD in the table. In this way, the user may be interrupted after each
buffer, after a specific buffer has been transmitted, or after each frame.
To rearrange the transmit queue before the SC302 has completed transmission of all
buffers, issue the STOP TRANSMIT command. This technique can be useful for
transmitting expedited data before previously linked buffers or for error situations. When
receiving the STOP TRANSMIT command, the HDLC controller will abort the current frame
being transmitted and start transmitting idles or flags. When the HDLC controller is given the
RESTART TRANSMIT command, it resumes transmission.
4.5.10.2 HDLC CHANNEL FRAME RECEPTION PROCESSING.
The HDLC receiver is
also designed to work with almost no intervention from the host. The HDLC receiver can
perform address recognition and CRC checking. The received frame (all fields between the
opening and closing flags) is made available to the user for performing any HDLC-based
protocol.
When the host enables one of the receivers, the receiver waits for an opening flag character.
When the receiver detects the first byte of the frame, the HDLC controller will compare the
frame address against the user-programmable addresses. The user has four 16-bit address
registers and an address mask available for address matching. The HDLC controller will
compare the received address field to the user-defined values after masking with the
address mask. The HDLC controller can also detect broadcast (all ones) addressed frames,
if one address register is written with all ones.
If a match is detected, the HDLC controller will open a new BD (if there is free place in the
Rx chunk) and will start to transfer the incoming frame to the BD's associated data buffer
starting with the first address byte. When the data buffer has been filled, the HDLC controller
clears the empty bit in the BD. If the incoming frame exceeds the length of the data buffer,
the HDLC controller will open the next BD right after the previous buffer and will continue to
transfer the rest of the frame to this BD's associated data buffer.
When the frame ends, the CRC field is checked against the recalculated value and is written
to the data buffer starting with the first address byte. The HDLC controller then sets the last
buffer in frame bit, writes the frame status bits into the BD, and clears the empty bit. The
HDLC controller next generates a maskable interrupt, indicating that a frame has been
received and is in memory. The HDLC controller then waits for a new frame. Back-to-back
frames may be received with only a single shared flag between frames. Also, flags that
share a zero will be recognized as two consecutive flags.
4.5.10.3 HDLC MEMORY MAP.
When configured to operate in HDLC mode, the SC302
overlays the structure shown in Table 4-4 onto the protocol-specific area of that SCC
parameter RAM. Refer to Table 4-3 for the placement of the SCC parameter RAM areas and
the other protocol specific parameter RAM values.
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