Table of Contents
Paragraph
Number
4.5.3
4.5.4
4.5.5
4.5.5.1
4.5.5.2
4.5.5.3
4.5.5.4
4.5.5.5
4.5.5.6
4.5.5.7
4.5.5.8
4.5.5.9
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.5.10.1
4.5.10.2
4.5.10.3
4.5.10.4
4.5.10.5
4.5.10.6
4.5.10.7
4.5.10.8
4.5.10.9
4.5.10.10
4.5.10.11
4.5.11
4.5.11.1
4.5.11.2
4.5.11.3
4.5.11.4
4.5.11.5
4.5.11.6
4.5.11.7
4.5.11.8
4.5.11.9
4.5.11.10
4.5.12
4.5.12.1
4.5.12.2
4.5.12.3
4.6
4.6.1
Title
Page
Number
viii
MC68SC302 USER’S MANUAL
MOTOROLA
SCC Transmit Buffer Descriptors...........................................................4-18
SCC Receive Buffer Descriptors............................................................4-19
SCC Parameter RAM.............................................................................4-23
RX BD Table Pointer (RBASE)..............................................................4-23
RX Chunk Length (RLEN)......................................................................4-23
RX Interrupt Threshold (RTHRSH) ........................................................4-23
CPU First Not Handled BD (RNH) .........................................................4-23
RX Time-OUT(RTO) ..............................................................................4-23
Maximum Receive Buffer Length Register (MRBLR) ............................4-24
RX Current BD (RCBD) .........................................................................4-24
TX BD Table Pointer (TBASE)...............................................................4-24
Transmitter Buffer Descriptor Pointer (TBPTR) .....................................4-24
SCC Event Register (SCCE) .................................................................4-25
SCC Mask Register (SCCM) .................................................................4-25
SCC Status Register (SCCS) ................................................................4-26
Disabling the SCCs................................................................................4-26
HDLC Controller.....................................................................................4-27
HDLC Channel Frame Transmission Processing ..................................4-28
HDLC Channel Frame Reception Processing .......................................4-29
HDLC Memory Map ...............................................................................4-29
HDLC Programming Model....................................................................4-30
HDLC Command Set.............................................................................4-30
HDLC Address Recognition...................................................................4-31
HDLC Error-Handling Procedure ...........................................................4-31
HDLC Receive Buffer Descriptor (Rx BD) .............................................4-32
HDLC Transmit Buffer Descriptor (TxBD)..............................................4-33
HDLC Event Register.............................................................................4-35
HDLC Mask Register.............................................................................4-36
Transparent Controller...........................................................................4-36
Transparent Channel Buffer Transmission Processing .........................4-36
Transparent Channel Buffer Reception Processing...............................4-37
Transparent Memory Map......................................................................4-38
Transparent Commands........................................................................4-38
Transparent Synchronization.................................................................4-39
Transparent Error-Handling Procedure..................................................4-39
Transparent Receive Buffer Descriptor (RxBD).....................................4-40
Transparent Transmit Buffer Descriptor (TxBD) ....................................4-41
Transparent Event Register...................................................................4-42
Transparent Mask Register....................................................................4-43
SCC2/3 Clocking in NMSI mode............................................................4-43
SCC2/3 NMSI Interface .........................................................................4-43
SCC2/3 CODEC Interface .....................................................................4-43
Configuration Register (SCON) .............................................................4-44
Serial Communication Port (SCP) .........................................................4-47
SCP Programming Model......................................................................4-47