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參數(shù)資料
| 型號(hào)： | ML53612 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange |
| 中文描述： | 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時(shí)隙交換 |
| 文件頁(yè)數(shù)： | 20/68頁(yè) |
| 文件大小： | 696K |
| 代理商： | ML53612 |
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ML53612
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16
Oki Semiconductor
5.4 Configuration Registers
Note: All "Reserved" configuration registers should be written "0".
Configuration Register Byte 0, AR = 0000h
DR_0
C
Definition
0
0
Diagnostic Mode
1
1
Test Mode
2
2
APLL Power-down Mode
3
3
APLL Bypass Mode
[7:4]
[7:4]
APLL CLKREF Frequency [3:0]
Diagnostic Mode (C_ [0]) (Read/Write)
Set to 0 for normal operation
0
→
Diagnostic Mode Disabled
1
→
Diagnostic Mode Enabled (Default)
Test Mode (C_ [1]) (Read/Write)
Enables testing with the slave DPLL bypassed. Set to 0 for normal operation.
0
→
Test Mode Disabled (Default)
1
→
Test Mode Enabled
APLL Power-down Mode (C_ [2]) (Read/Write)
Powers down analog PLL, resets APLL charge pump. Set to 0 for normal operation.
0
→
APLL Power-down Mode Disabled
1
→
APLL Power-down Mode Enabled (Default)
APLL Bypass Mode (C_ [3]) (Read/Write)
APLL Bypass used during simulation and testing. Set to 0 for normal operation.
0
→
APLL Bypass Mode Disabled
1
→
APLL Bypass Mode Enabled (Default)
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