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參數(shù)資料
| 型號： | ML53612 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange |
| 中文描述： | 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時隙交換 |
| 文件頁數(shù)： | 50/68頁 |
| 文件大?。?/td> | 696K |
| 代理商： | ML53612 |
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ML53612
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Oki Semiconductor
Note: When converted from parallel to serial, TDM Data Bit 1 is transmitted first.
Note: When converted from parallel to serial, TDM Data Bit 1 is transmitted first.
5.10 Indirect Transmit Switch Parallel Access Registers, AR = 403fh:4000h (Ch. 63:0)
DR_0
Definition
[7:0]
TDM Data [1:8]
TDM Data [1:8] (Read/Write)
Writing to this register provides the transmit data when the transmit switch channel is configured to use parallel microprocessor data as its source (to
CT_D). This register and the serial input buffer share common hardware, therefore this register must be written after the transmit switch channel
source is changed from serial TDM data to parallel microprocessor data.
The transmit switch channel output buffer data obtained by reading the TDM data register. When the transmit switch channel is configured to use serial
TDM data as its source, the data from the local SI channel can be monitored. When the transmit switch channel is configured to use parallel
microprocessor data as its source, the data written into this register can be monitored.
5.11 Indirect Receive Switch Parallel Access Registers, AR = 503fh:5000h (Ch. 63:0)
DR_0
Definition
[7:0]
TDM Data [1:8]
TDM Data [1:8] (Read/Write)
Writing to this register provides the receive data when the receive switch channel is configured to use parallel microprocessor data as its source (to
L_SO). This register and the serial input buffer share common hardware, so this register must be written after the receive switch channel source is
changed from serial TDM data to parallel microprocessor data.
The receive switch channel output buffer data is obtained by reading the TDM Data register. When the receive switch channel is configured to use serial
TDM data as its source, the data from the CT_D stream and time-slot selected in the receive switch routing registers can be monitored. When the
receive switch channel is configured to use parallel microprocessor data as its source, the data written into this register can be monitored.
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