參數(shù)資料
型號(hào): ML53612
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange
中文描述: 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時(shí)隙交換
文件頁數(shù): 37/68頁
文件大?。?/td> 696K
代理商: ML53612
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I
ML53612
I
33
Oki Semiconductor
Configuration Register Byte 16, AR = 0010h
DR_0
C
Definition
0
128
CT Bus A Error Latch
1
129
CT Bus B Error Latch
2
130
SCbus Error Latch
3
131
MVIP Error Latch
4
132
Master PLL Error Latch
5
133
Frame Boundary Latch
6
134
Reserved
7
135
Reserved
CT Bus A Error Latch (C_ [128]) (Read Only)
0
1
CT Bus A Error Latch False
CT Bus A Error Latch True
CT Bus B Error Latch (C_ [129]) (Read Only)
0
1
CT Bus B Error Latch False
CT Bus B Error Latch True
SCbus Error Latch (C_ [130]) (Read Only)
0
1
SCbus Error Latch False
SCbus Error Latch True
MVIP Error Latch (C_ [131]) (Read Only)
0
1
MVIP Error Latch False
MVIP Error Latch True
Master PLL Error Latch (C_ [132]) (Read Only)
0
1
Master PLL Error Latch False
Master PLL Error Latch True
Frame Boundary Latch (C_ [133]) (Read Only)
0
1
Frame Boundary Latch False
Frame Boundary Latch True
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