參數(shù)資料
型號(hào)： ML53612
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange
中文描述： 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時(shí)隙交換
文件頁(yè)數(shù)： 57/68頁(yè)
文件大?。?/td> 696K
代理商： ML53612
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I
ML53612
I
53
Oki Semiconductor
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Local Clock and Frame Synchronization Timing
[1]
[2]
Local Serial Stream Timing
[1]
1.
2.
Timing measured with 100 pF load on all Local bus outputs.
L_CLK and L_FS shown with positive polarity, timing is equivalent when signals are inverted.
Parameter
Symbol
Min
Typ
Max
Unit
L_CLK period (2.048 MHz)
t1a
488
ns
L_CLK period (4.096 MHz)
t1b
244
ns
L_CLK period (8.192 MHz)
t1c
122
ns
L_CLK period (16.384 MHz)
t1d
61
ns
L_FS delay from L_CLK _ (Early position)
t2
-10
+10
ns
L_FS delay from L_CLK _ (Straddle position)
t3
-10
+10
ns
L_FS delay from L_CLK _ (Late position)
t4
-10
+10
ns
Local Clock to CT Bus Clock Skew
[1]
1.
When reference L_CLK is more stable, there is no reduction in the amplitude of the skew, but a reduction in the number of occurrences. The further
away from the center frequency, the more frequently the skew occurs. The skew amplitude will jump in steps, but the range will remain the same.
Test conditions were 65.536 MHz (C_[7:4]= 0) and 2.048 MHz (C_[7:4] = 6).
Parameter
Symbol
Min
Typ
Max
Unit
With C_11 (Advance Slave DPLL Timing) set to 0 (default)
t5
+22.5 / -0
Ns
With C_11 (Advance Slave DPLL Timing) set to 1
t5
+15 / -7.5
Ns
1.
The Bit Cell Boundary is defined by the relative edge of L_CLK (Figure 11assumes that L_CLK and L_FS polarities are both non-inverted
(C_[76] = 0; C_[77] = 0; C_[84] = 0; C_[85] = 0))
Parameter
Symbol
Min
Typ
Max
Unit
L_SO float to valid delay from Bit Cell Boundary
t6
-10
+10
ns
L_SO valid to valid delay from Bit Cell Boundary
t7
-10
+10
ns
L_SO valid to float delay from Bit Cell Boundary
t8
-10
+10
ns
2,048Mb/s Sample Point from Bit Cell Boundary
t9a
+335.5
ns
4,096Mb/s Sample Point from Bit Cell Boundary
t9b
+213.5
ns
8.192Mb/s Sample Point from Bit Cell Boundary
t9c
+91.5
ns
L_SI Setup to Sample Point
t10
10
ns
L_SI Hold to Sample Point
t11
10
ns
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