參數(shù)資料
型號: ML53612
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange
中文描述: 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時隙交換
文件頁數(shù): 49/68頁
文件大?。?/td> 696K
代理商: ML53612
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ML53612
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45
Oki Semiconductor
Note: Do not use Minimum delay mode on channels using parallel data source.
Note: When Local Connect is Enabled, the Receive Switch routing registers DR_0 is redefined as the 6 bits of the
transmit channel number instead of the CT_D time-slot, as shown below:
Note: The Serial TDM data and the parallel access register share common registers within the receive switch.
Therefore it is necessary to write to the parallel access register after the source is changed to parallel
microprocessor data.
DR_2
Definition
0
Delay
1
Local Connect
2
Source
[7:3]
Reserved (write zero)
Delay (Read/Write)
Selects the switching delay mode. When set to Constant, data is switched on frame boundaries resulting in a constant 1 frame delay and allowing
"bundling". When set to Minimum, data is switched on 2 Mbps time-slot boundaries reducing the delay through the switch for certain combinations of
input to output time-slots.
0
Constant (Default)
1
Minimum
Local Connect Enable (Read/Write)
Enables the receive switch to be used for local connection. When enabled, a transmit channel is connected to a receive channel without using the CT
Bus.
0
Local Connect Disabled (Default)
1
Local Connect Enabled
DR_0_[5:0]
Transmit channel bits [5:0]
Source (Read/Write)
Selects the receive channel data source. When set to 0, Serial TDM data from the CT Bus data stream or transmit channel (see Local Connect Enable)
is selected. When set to 1, the channels parallel access register is selected as the source of the receive channel data.
0
Serial TDM data (Default)
1
Parallel microprocessor data
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