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參數(shù)資料
| 型號： | ML53612 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange |
| 中文描述： | 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時隙交換 |
| 文件頁數(shù)： | 30/68頁 |
| 文件大?。?/td> | 696K |
| 代理商： | ML53612 |
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ML53612
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26
Oki Semiconductor
Configuration Register Byte 9, AR = 0009h
DR_0
C
Definition
[1:0]
[73:72]
L_SI_[1:0], L_SO_[1:0] Stream Rate [1:0]
[3:2]
[75:74]
L_CLK_0 Frequency [1:0]
4
76
L_CLK_0 Polarity
5
77
L_FS_0 Polarity
[7:6]
[79:78]
L_FS_0 Position [1:0]
L_SI_[1:0], L_SO_[1:0] Stream Rate [1:0] (C_ [73:72]) (Read/Write)
00
01
10
11
→
→
→
→
2.048 Mbps (L_SI_[1:0], L_SO_[1:0]) (Default)
4.096 Mbps (L_SI_[0], L_SO_[0])
8.192 Mbps (L_SI_[0], L_SO_[0])
Reserved
L_CLK_0 Frequency [1:0] (C_ [75:74]) (Read/Write)
[1]
1.
Note: the L_CLK_0 frequency need not match the L_SI and L_SO stream frequencies, neither need it match the CT_C8 frequency when configured
as slave-to-CT.
00
01
10
11
→
→
→
→
2.048 MHz (Default)
4.096 MHz
8.192 MHz
16.384 MHz
L_CLK_0 Polarity (C_ [76]) (Read/Write)
0
1
→
→
L_CLK_0 Non-Inverted (Default)
L_CLK_0 Inverted
L_FS_0 Polarity (C_ [77]) (Read/Write)
0
1
→
→
L_FS_0 Non-Inverted (Default)
L_FS_0 Inverted
L_FS_0 Position [1:0] (C_ [79:78]) (Read/Write)
00
01
10
11
→
→
→
→
Early - L_FS_0 occurs during the last L_CLK_0 period of the frame (Default)
Straddle - L_FS_0 straddles the frame boundary
Late - L_FS_0 occurs during the first L_CLK_0 period of the frame
Reserved
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