參數(shù)資料
型號(hào)： ML53612
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange
中文描述： 64通道全雙工H.100/H.110 CT總線系統(tǒng)接口和時(shí)隙交換
文件頁(yè)數(shù)： 35/68頁(yè)
文件大?。?/td> 696K
代理商： ML53612
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I
ML53612
I
31
Oki Semiconductor
Configuration Register Byte 14, AR = 000eh
[1]
1.
Masking an interrupt disables that interrupt from being OR’ed together with other interrupts to the INT pin. The state of the latches are accessible
while masked (polling mode).
DR_0
C
Definition
0
112
CT Bus A Error Interrupt Mask
1
113
CT Bus B Error Interrupt Mask
2
114
SCbus Error Interrupt Mask
3
115
MVIP Error Interrupt Mask
4
116
Master PLL Error Interrupt Mask
5
117
Frame Boundary Interrupt Mask
6
118
Reserved
7
119
Reserved
CT Bus A Error Interrupt Mask (C_ [112]) (Read/Write)
0
1
→
→
CT Bus A Error Interrupt Unmasked
CT Bus A Error Interrupt Masked (Default)
CT Bus B Error Interrupt Mask (C_ [113]) (Read/Write)
0
1
→
→
CT Bus B Error Interrupt Unmasked
CT Bus B Error Interrupt Masked (Default)
SCbus Error Interrupt Mask (C_ [114]) (Read/Write)
0
1
→
→
SCbus Error Interrupt Unmasked
SCbus Error Interrupt Masked (Default)
MVIP Error Interrupt Mask (C_ [115]) (Read/Write)
0
1
→
→
MVIP Error Interrupt Unmasked
MVIP Error Interrupt Masked (Default)
Master PLL Error Interrupt Mask (C_ [116]) (Read/Write)
0
1
→
→
Master PLL Error Interrupt Unmasked
Master PLL Error Interrupt Masked (Default)
Frame Boundary Interrupt Mask (C_ [117]) (Read/Write)
0
1
→
→
Frame Boundary Interrupt Unmasked
Frame Boundary Interrupt Masked (Default)
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