參數(shù)資料
型號(hào): MM908E622ACDWB
廠商: Freescale Semiconductor
文件頁數(shù): 12/63頁
文件大?。?/td> 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動(dòng)鏡像控制
核心處理器: HC08
程序存儲(chǔ)器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
908E622
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
M68H
C08
C
P
U
ALU
PORT B
DDRB
PTB0/AD0
ADOUT
Analog
Multiplexer
Analog
Port
with
Current
Source
CPU
Registers
DDRE
PORT E
PTE1/RXD
PTE0/TXD
PTB1/AD1
PTB2/AD2
PTB3/AD3
PTB4/AD4
PTB5/AD5
PTB6/AD6/TBCH0
PTB7/AD7/TBCH1
DDRD
PORT D
PTD1/TACH1
PTD0/TACH0
PORT C
DDRC
PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO
BEMF
Module
Prescaler
Module
Arbiter
Module
Periodic
Wake-up
Timebase
Module
Configuration
Register
Module
Serial
Peripheral
Interface
Module
Computer
Operating
Properly
Module
Enhanced
Serial
Communication
Interface
Module
2-channel
Timer
Interface
Module
B
2-channel
Timer
Interface
Module
A
5-Bit
Keyboard
Interrupt
Module
Single
Breakpoint
Break
Module
DDRA
PORT A
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
PTA5/SPSCK
PTA6/SS
Security
Module
Power-ON
Reset
Module
POWER
VSS
VDD
10
Bit
Analog-to-
Digital
Converter
Module
VSSA
VREFL
VDDA
VREFH
Single
External
IRQ
Module
IRQ
24
Internal
System
Integration
Module
RST
Internal
Clock
Generator
Module
OSC1
OSC2
User
Flash
Vector
Space,
36
Bytes
Flash
programming
(Burn-in),
1024
Bytes
Monitor
ROM,
310
Bytes
User
RAM,
512
Bytes
User
Flash,
15,872
Bytes
Control
and
Status
Register,
64
Bytes
Internal Bus
FLSVPP
PTD1/TACH1
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
VDDA/VREFH
EVDD
EVSS
VSSA/VREFL
RST
IRQ
RST_A
IRQ_A
PTE1/RXD
PTD0/TACH0
LIN
TESTMODE
VSUP[1:8]
GND[1:4]
PTB0/AD0
PTA5/SPSCK
SPSCK
MOSI
PTC1/MOSI
MISO
PTC0/MISO
SS
PWM
PTA6/SS
PTD0/TACH0
PTE0/TXD
PTE1/RXD
RXD
TXD
SPI
&
CONTROL
Hallport
EC
glass
Driver
&
Diagnostic
Half
Bridge
Driver
&
Diagnostic
Half
Bridge
Driver
&
Diagnostic
Half
Bridge
Driver
&
Diagnostic
Half
Bridge
Driver
&
Diagnostic
High
Side
Driver
&
Diagnostic
High
Side
Driver
&
Diagnostic
High
Side
Driver
&
Diagnostic
Autonomous
Watchdog
Reset
Control
LIN
Physical
Layer
Wakeup
Port
Voltage
Regulator
Switched
VDD
Driver
&
Diagnostic
A0CST
A0
H0
EC
ECR
HB4
HB3
HB2
HB1
HS3
HS2
HS1[a:b]
L0
HVDD
VDD
VSS
Fig
u
re
2
.90
8E622
Simplif
ie
d
In
tern
al
B
lo
ck
Diag
ram
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