OPERATIONAL MODES The EC output is protect" />
參數(shù)資料
型號(hào): MM908E622ACDWB
廠商: Freescale Semiconductor
文件頁數(shù): 38/63頁
文件大?。?/td> 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動(dòng)鏡像控制
核心處理器: HC08
程序存儲(chǔ)器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
908E622
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The EC output is protected against shorts to GND. In case
of a short-circuit, the ECOCF in the EC Status and the
Control Register (ECSCTL) are set, and the EC circuitry is
disabled.
EC Digital to Analog Converter
The EC output, and therefore the voltage on the EC glass
are controlled. The EC glass circuitry has a 6-bit D/A
converter to control the output voltage between 0 and 1.4 V.
EC D/A Converter Control Register (ECDACC)
ECDAx — Digital to Analog Bits
These read/write bits set the output voltage on the EC pin.
EC Status and Control Register (ECSCTL)
ECON — Electrochrome Circuitry Enable Bit
This read/write bit enables transistor T2 of the
electrochrome circuitry. Reset clears the ECON bit.
1 = T2 EC circuitry enabled
0 = T2 EC circuitry disabled
ECOLT — Electrochrome Circuitry Open Load Test Bit
This read/write bit enables the open load test for the
electrochrome circuitry. If this bit is set, the EC Glass
functionality is ceased. Reset clears the ECOLT bit.
1 = EC Open Load circuitry enabled
0 = EC Open Load circuitry disabled
ECRON — EC Resistor enable Bit
This read/write bit enables transistor T1 of the
electrochrome circuitry. Reset clears the ECRON bit.
1 = T1 EC circuitry enabled
0 = T1 EC circuitry disabled
Note: Controlling the output voltage on pin EC is done by
transistor T2 only. The enable of T1 will switch the VSUP
voltage via the external EC resistor to the EC glass.
ECOCF — EC Output Over-current Flag Bit
This read/write flag is set on short-circuit conditions at the
EC output (short to VSUP/ short to GND). Clear ECOCF and
enable the EC circuitry by writing a logic [1] to ECOCF.
Writing a logic [0] to ECOCF has no effect. Reset clears the
ECOCF bit.
1 = short-circuit condition on EC output detected
0 = no short-circuit condition on EC output detected
ECOLF — EC Open Load Flag Bit
This read/write flag is set on an open load condition of the
EC output. Clear ECOLF and disable the EC circuitry by
writing a logic [1] to ECOLF. Writing a logic [0] to ECOLF has
no effect. Reset clears the ECOLF bit.
1 = open load condition on EC output detected
0 = no open load condition on EC output detected
System Control Register (SYSCTL)
PSON — Power Stages On Bit
This read/write bit enables the power stages (half-bridges,
high sides, LIN transmitter, A0 Current Sources, and HVDD
output). Reset clears the PSON bit.
1 = power stages enabled
0 = power stages disabled
STOP — Change to STOP Mode Bit
This write bit instructs the chip to enter Stop mode (See
Operational Modes on page 25). Reset or CPU interrupt
requests clear the STOP bit.
1 = go to Stop mode
0 = not in stop mode
In order to safely enter Stop mode, all other bits (Bit7-Bit2)
have to be “0”. Otherwise, the STOP command will not be
executed.
SLEEP — Change to SLEEP Mode Bit
This write bit instructs the chip to enter Sleep mode (See
Operational Modes on page 25). Reset or CPU interrupt
requests clear the SLEEP bit.
1 = go to Sleep mode
0 = not in sleep mode
In order to safely enter Sleep mode, all other bits (Bit7-
Bit2) have to be “0”. Otherwise the SLEEP command will not
be executed.
Register Name and Address: ECDACC - $06
Bit7
6
5
4
3
2
1
Bit0
Read
0
ECD
A5
ECD
A4
ECD
A3
ECD
A2
ECD
A1
ECD
A0
Write
Reset
0
Register Name and Address: ECSCTL - $05
Bit7
6
5
4
3
2
1
Bit0
Read
ECO
N
ECO
LT
ECR
ON
0
ECO
CF
ECO
LF
Write
Reset
0
Register Name and Address: SYSCTL - $00
Bit7
6
5
4
3
2
1
Bit0
Read
PSON
00
HTIS1
HTIS0
VIS
SRS1
SRS0
Write
STOP
SLEEP
Reset
0
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