LOGIC COMMANDS AND REGISTERS WDRST - Watch" />
參數(shù)資料
型號: MM908E622ACDWB
廠商: Freescale Semiconductor
文件頁數(shù): 41/63頁
文件大小: 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標準包裝: 26
應(yīng)用: 自動鏡像控制
核心處理器: HC08
程序存儲器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
46
Freescale Semiconductor
908E622
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
WDRST - Watchdog Reset Bit
This write only bit resets the Watchdog. Write a logic [1] to
reset the watchdog timer.
1 = Reset WD and restart timer
0 = no effect
Voltage Regulator
The 908E622 contains a low power, low drop voltage
regulator to provide internal power and external power for the
MCU. The on-chip regulator consist of two elements, the
main regulator, and the low voltage reset circuit.
The VDD regulator accepts an unregulated input supply
and provides a regulated VDD supply to all digital sections of
the device. The output of the regulator is also connected to
the VDD pin to provide the 5.0 V to the microcontroller.
Run Mode
During RUN mode, the main voltage regulator is on. It will
provide a regulated supply to all digital sections.
STOP Mode
During STOP mode, the Stop mode regulator will take care
of suppling a regulated output voltage. The Stop mode
regulator has a limited output current capability.
SLEEP Mode
In Sleep mode, the main voltage regulator external VDD is
turned off and the LVR circuitry will force the RST_A pin low.
LOGIC COMMANDS AND REGISTERS
908E622 SERIAL PHERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) creates the
communication link between the MCU and the analog die.
The interface consists of four pins
MOSI - Master Out Slave In (internal pull-down)
MISO - Master In Slave Out
SPSCK - Serial Clock (internal pull-down)
SS - Slave Select (internal pull-up)
A complete data transfer via the SPI, consists of 2 bytes.
The master sends address and data, the slave returns
system status and the data of the selected address.
Figure 31. SPI Protocol
During the inactive phase of SS, the new data transfer will
be prepared. The falling edge on the SS line, indicates the
start of a new data transfer (framing) and puts MISO in the
low-impedance mode. The first valid data is moved to
MISO with the rising edge of SPSCK.
The MOSI and MISO will change data on a rising edge of
SPSCK.
The MOSI and MISO will be sampled on a falling edge of
SPSCK.
The data transfer is only valid, if exactly 16 sample clock
edges are present in the active phase of SS.
After a write operation the transmitted data will be latched
into the register, by the rising edge of SS.
1
0
20 ms window watchdog period
1
10 ms window watchdog period
Table 12. Watchdog Period Selection Bits
WDP1
WDP0
Mode
S7
S6
S5
S4
S3
S2
S1
S0
R/W
A4
A3
A2
A1
A0
P
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
System Status Register
Read/Write, Address, Parity
Data (Register write)
Data (Register read)
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
SS
MOSI
MISO
SPSCK
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