LOGIC COMMANDS AND REGISTERS Register rea" />
參數(shù)資料
型號: MM908E622ACDWB
廠商: Freescale Semiconductor
文件頁數(shù): 42/63頁
文件大小: 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標準包裝: 26
應用: 自動鏡像控制
核心處理器: HC08
程序存儲器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 管件
供應商設備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
908E622
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Register read data is internally latched into the SPI, at the
time when the parity bit is transferred
SS high will force MISO to a high-impedance
Master Address Byte
A4 - A0
includes the address of the desired register.
R/W
includes the information if it is a read or a write operation.
If R/W = 1 (read operation), second byte of master
contains no valid information, slave just transmits back
register data.
If R/W = 0 (write operation), master sends data to be
written in the second byte, slave sends concurrently
contents of selected register prior to write operation, write
data is latched in the SMARTMOS registers on rising edge
of SS.
Parity P
completes the total number of 1 bits of (R/W,A[4-0]) to an
even number. e.g. (R/W,A[4-0]) = 100001 -> P0 = 0.
The parity bit is only evaluated during write operations and
ignored for read operations.
Bit X
not used
Master Data Byte
This byte includes data to be written or no valid data during
a read operation.
Slave Status Byte
This byte always includes the contents of the system
status register ($0C), independent if it is a write or read
operation, or which register was selected.
Slave Data Byte
This byte includes the contents of selected register, during
write operation in includes the register content prior to write
operation.
SPI REGISTER OVERVIEW
Table 13 SUMMARIZES THE SPI REGISTER ADDRESSES AND THE BIT NAMES OF EACH REGISTER.
Table 13. SPI Register Overview
Addr
Register Name
R/W
Bit
76
5
4
3
2
1
0
$00
System Control
(SYSCTL)
R
PSON
0
HTIS1
HTIS0
VIS
SRS1
SRS0
W
STOP
SLEEP
$01
Half-bridge Output
(HBOUT)
R
HB4_H
HB4_L
HB3_H
HB3_L
HB2_H
HB2_L
HB1_H
HB1_L
W
$02
High Side Output
(HSOUT)
R
HVDDON
0
HS3PWM
HS2PWM
HS1PWM
HS3ON
HS2ON
HS1ON
W
$03
Half-bridge Status and
Control (HBSCTL)
R
CRM
0
HB4OCF
HB3OCF
HB2OCF
HB1OCF
W
$04
High Side Status and
Control (HSSCTL)
R
HVDDOCF
0
HS3OCF
HS2OCF
HS1OCF
W
$05
EC Status and Control
(ECSCTL)
R
ECON
ECOLT
ECRON
0
ECOCF
ECOLF
W
$06
EC Digital to Analog
Control (ECDACC)
R
0
ECDAC5
ECDAC4
ECDAC3
ECDAC2
ECDAC1
ECDAC0
W
$07
H0/L0 Status and
Control (HLSCTL)
R
L0F
0
H0OCF
H0F
H0EN
H0PD
H0MS
W
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