參數(shù)資料
型號(hào): MM908E622ACDWB
廠商: Freescale Semiconductor
文件頁數(shù): 49/63頁
文件大?。?/td> 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動(dòng)鏡像控制
核心處理器: HC08
程序存儲(chǔ)器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
53
908E622
TYPICAL APPLICATIONS
.
Figure 33. Normal Monitor Mode Circuit
Table 23 summarizes the possible configurations and the
necessary setups.
EMC/EMI RECOMMENDATIONS
This paragraph gives some device specific
recommendations to improve EMC/EMI performance.
Further generic design recommendations can be e.g. found
on the Freescale web site www.freescale.com.
VSUP Pins (VSUP[1:8])
Its recommended to place a high quality ceramic
decoupling capacitor close to the VSUP pins to improve
EMC/EMI behavior.
MM908E622
RST_A
RST
IRQ_A
IRQ
VSSA/VREFL
VDDA/VREFH
EVDD
VDD
EVSS
VSS
VSUP[1:8]
GND[1:4]
4.7F
100nF
PTC4/OSC1
PTB3/AD3
PTB4/AD4
PTA0/KBD0
PTA1/KBD1
TESTMODE
MAX232
10k
RS232
DB-9
1
3
C1+
C1-
4
5
C2+
C2-
7
8
2
3
5
VCC
GND
16
15
2
V+
V-
6
1F
+
1F
+
1F
+
1F
2
1
3
65
4
74HC125
9.8304MHz CLOCK
VDD
DATA
CLK
VDD
10k
VDD
VTST
VSUP
47F
+
100nF
10
9
T2OUT
R2IN
T2IN
R2OUT
Table 23. Monitor Mode Signal Requirements and Options
Mode
IRQ RST
TEST
MODE
Reset
Vector
Serial
Communication
Mode
Selection
ICG
COP
Normal
Request
Time-out
Communication Speed
PTA0
PTA1
PTB3
PTB4
External
Clock
Bus
Frequency
Baud
Rate
Normal
Monitor
VTST VDD
1
X
1
0
1
OFF
disabled
9.8304
MHz
2.4576 MHz
9600
Forced
Monitor
VDD
1
$FFFF
(blank)
10
X
OFF
disabled
9.8304
MHz
2.4576 MHz
9600
GND
ON
disabled
Nominal
1.6MHz
Nominal
6300
User
VDD
0
not $FFFF
(not blank)
X
ON
enabled
Nominal
1.6MHz
Nominal
6300
Notes
34.
PTA0 must have a pullup resistor to VDD in monitor mode
35.
External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1
36.
Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
37.
X = don’t care
38.
VTST is a high voltage VDD + 3.5 V VTST VDD + 4.5 V
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