OPERATIONAL MODES H0IE - H0 Input Inter" />
參數(shù)資料
型號(hào): MM908E622ACDWB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 22/63頁(yè)
文件大?。?/td> 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動(dòng)鏡像控制
核心處理器: HC08
程序存儲(chǔ)器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
908E622
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
H0IE - H0 Input Interrupt Enable Bit
This read/write bit enables CPU interrupts by the Hallport
flag, H0IF. Reset clears the H0IE bit.
1 = interrupt requests from H0IF flag enabled
0 = interrupt requests from H0IF flag disabled
LINIE - LIN line Interrupt Enable Bit
This read/write bit enables CPU interrupts by the LIN flag,
LINIF. Reset clears the LINIE bit.
1 = interrupt requests from LINIF flag enabled
0 = interrupt requests from LINIF flag disabled
HTRD - High Temperature Reset Disable Bit
This read/write bit disables the high temperature reset
function. Reset clears the HTRD bit.
1 = high temperature reset is disabled
0 = high temperature reset is enabled
Note: Disabling of the high temperature reset can lead to
a destruction of the part, in cases of high temperature. This
bit was foreseen for test purposes only!
HTIE - High Temperature Interrupt Enable Bit
This read/write bit enables CPU interrupts by the high
temperature flag, HTIF. Reset clears the HTIE bit.
1 = interrupt requests from HTIF flag enabled
0 = interrupt requests from HTIF flag disabled
LVIE - Low Voltage Interrupt Enable Bit
This read/write bit enables CPU interrupts by the low
voltage flag, LVIF.Reset clears the LVIE bit.
1 = interrupt requests from LVIF flag enabled
0 = interrupt requests from LVIF flag disabled
HVIE - High Voltage Interrupt Enable Bit
This read/write bit enables CPU interrupts by the high
voltage flag, HVIF.Reset clears the HVIE bit.
1 = interrupt requests from HVIF flag enabled
0 = interrupt requests from HVIF flag disabled
PSFIE - Power Stage Fail Interrupt Enable Bit
This read/write bit enables CPU interrupts by power stage
fail flag, PSFIF. Reset clears the PSFIE bit.
1 = interrupt requests from PSFIF flag enabled
0 = interrupt requests from PSFIF flag disabled
RESETS
The 908E622 has four internal and one external reset
source.
Each internal reset event will cause a reset pin low for tRST
(1.25 ms typical), after the reset event is gone.
Figure 15. Internal Reset Routing
RSR
WDRE
WD Reset Sensor
VDD
RST_A
SPI REGISTERS
Reset SPI Register
(not RSR)
POR internal VREG
LVR Main VREG
HTRD
HTR Reset Sensor
MONO FLOP
Pulse Duration
after reset event is
removed
Clear RSR and set
POR Bit
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