LOGIC COMMANDS AND REGISTERS Optimal Clear" />
參數(shù)資料
型號： MM908E622ACDWB
廠商： Freescale Semiconductor
文件頁數(shù)： 44/63頁
文件大小： 0K
描述： IC QUAD HALF BRDG TRPL SW 54SOIC
標準包裝： 26
應(yīng)用： 自動鏡像控制
核心處理器： HC08
程序存儲器類型： 閃存（16 kB）
控制器系列： 908E
RAM 容量： 512 x 8
接口： SCI，SPI
輸入/輸出數(shù)： 12
電源電壓： 9 V ~ 16 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 54-BSSOP（0.295"，7.50mm 寬）裸露焊盤
包裝： 管件
供應(yīng)商設(shè)備封裝： 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
908E622
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Optimal Clear Interval
The optimal clear interval, meaning the clear interval with
the biggest possible variation to latest window open time, and
to the earliest window closed time, can be calculated with the
following formula:
t_opt = t_open + (t_open+t_closed) / 2
See Table 14 to select the optimal clear interval for the
watchdog based on the Window No. and chosen period.
Analog Die System Trim Values
For improved application performance, and to ensure the
outlined datasheet values, the analog die needs to be
trimmed. For this purpose, 3 trim values are stored in the
Flash memory at addresses $FDC4 - $FDC6. These values
have to be copied into the analog die SPI registers:
copy $FDC4 into SYSTRIM1 register $0F
copy $FDC5 into SYSTRIM2 register $10
copy $FDC6 into SYSTRIM3 register $11
Note: These values have to be copied to the respective
SPI register after a reset, to ensure proper trimming of the
device.
System Test Register (SYSTEST)
The System Test Register is reserved for production
testing and is not allowed to be written into.
System Trim Register 1 (SYSTRIM1)
HVDDT1:0 - HVDD Over-current Shutdown Delay Bits
These read/write bits allow changing the filter time (for
capacitive load) for the HVDD over-current detection.
Reset clears the HVDDT1:0 bits an sets the delay to the
maximum value.
Table 14. Window Clear Interval
Window
Range
Period Select
bits
Watchdog Period t_wd
Effective Open Window
Optimal Clear Interval
$FDCF
WDP1:0
min.
max.
Unit
t_open
t_closed
Unit
t_opt
Unit
max.
variation
0
00
68
92
ms
46
68
ms
57
ms
±19.3%
01
34
46
23
34
28.5
10
17
23
11.5
17
14.25
11
8.5
11.5
5.75
8.5
7.125
1
00
92
124
ms
62
92
ms
77
ms
±19.5%
01
46
62
31
46
38.5
10
23
31
15.5
23
19.25
11
11.5
15.5
7.75
11.5
9.625
2
00
52
68
ms
34
52
ms
43
ms
±20.9%
01
26
34
17
26
21.5
10
13
17
8.5
13
10.75
11
6.5
8.5
4.25
6.5
5.375
Register Name and Address: SYSTEST - $0E
Bit7
6
5
4
3
2
1
Bit0
Read
reser
ved
reser
ved
reser
ved
reser
ved
reser
ved
reser
ved
reser
ved
reser
ved
Write
Reset
0
Note: do not write to the reserved bits
Register Name and Address: IBIAS - $0F
Bit7
6
5
4
3
2
1
Bit0
Read
HVD
DT1
HVD
DT0
0
reser
ved
0
reser
ved
ITRI
M3
ITRI
M2
ITRI
M1
ITRI
M0
Write
Reset
0
Note: do not change (set) the reserved bits
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