參數(shù)資料
型號(hào)： MR80C32-25SBR
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)： 49/80頁(yè)
文件大?。?/td> 5152K
代理商： MR80C32-25SBR
249
XMEGA A [MANUAL]
8077I–AVR–11/2012
Table 21-9. SBMODE bit settings.
Bit 2:0 – CHSIZE[2:0]: Character Size
The CHSIZE[2:0] bits set the number of data bits in a frame according to Table 21-10. The receiver and transmitter use
the same setting
Table 21-10. CHSIZE bit settings.
Bit 2 – UDORD: Data Order
This bit is only for master SPI mode, and this bit sets the frame format. When written to one, the lsb of the data word is
transmitted first. When written to zero, the msb of the data word is transmitted first. The receiver and transmitter use the
same setting. Changing the setting of UDORD will corrupt all ongoing communication for both receiver and transmitter.
Bit 1 – UCPHA: Clock Phase
This bit is only for master SPI mode, and the bit determine whether data are sampled on the leading (first) edge or tailing
(last) edge of XCKn. Refer to the “Master SPI Mode Clock Generation” on page 235 for details.
21.15.6 BAUDCTRLA – Baud Rate register A
Bit 7:0 – BSEL[7:0]: Baud Rate bits
These are the lower 8 bits of the 12-bit BSEL value used for USART baud rate setting. BAUDCTRLB contains the four
most-significant bits. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed.
Writing BSEL will trigger an immediate update of the baud rate prescaler. See the equations in Table 21-1 on page 233.
SBMODE
Stop Bit(s)
0
1
2
CHSIZE[2:0]
Group configuration
Character Size
000
5BIT
5-bit
001
6BIT
6-bit
010
7BIT
7-bit
011
8BIT
8-bit
100
–
Reserved
101
–
Reserved
110
–
Reserved
111
9BIT
9-bit
Bit
7
654321
0
+0x06
BSEL[7:0]
Read/Write
R/W
Initial Value
0
000000
0
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