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參數(shù)資料
| 型號： | MR80C32-25SBR |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 69/80頁 |
| 文件大?。?/td> | 5152K |
| 代理商： | MR80C32-25SBR |
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269
XMEGA A [MANUAL]
8077I–AVR–11/2012
Figure 24-9. Three-Port SDRAM configuration.
24.7.3 Timing
The Clock Enable (CKE) signal is required for SDRAM when the EBI is clocked at 2x the CPU clock speed.
24.7.4 Initialization
Configuring Chip Select 3 to SDRAM will enable the initialization of the SDRAM. The Load Mode Register command is
automatically issued at the end of the initialization. For correct information to be loaded to the SDRAM, one of the
following must be done:
1. Configure the SDRAM control registers before enabling chip select 3 to SDRAM
2. Issue a Load Mode Register command, and perform a dummy access after the SDRAM is initialized
The SDRAM initialization is not interruptible by other EBI accesses.
24.7.5 Refresh
The EBI will automatically handle the SDRAM refresh as long as the refresh period is configured. On average will one
refresh command be issues at the interval given by the SDRAM Refresh Period Register. The EBI can collect up to four
refresh commands in case the interface is busy on another chip select or in the middle of a read/write at the time a
refresh should have been performed.
24.8
I/O Pin and Pin-out Configuration
When the EBI is enabled, it will override the direction and/or value of the I/O pins where the EBI data lines are placed.
The EBI will also override the value, but not the direction, of the I/O pins where the EBI address and control lines are
placed. These I/O pins must be configured to output when the EBI is used. I/O pins for unused EBI address and control
lines can be used as normal I/O pins or for other alternate functions on the pins.
For control signals that are active-low, the pin output value should be set to one (high). For control signals that are active-
high, the pin output value should be set to zero (low). Address lines do not require specific pin output value configuration.
The chip select lines should have pull-up resistors to ensure that they are kept high during power on and reset. If a chip
select line is active-high, a pull-down resistor should be used instead of a pull-up.
For more details on I/O pin configuration, refer to “I/O Ports” on page 132.
The tables below summaries the actual port pin-out for the various SRAM and SDRAM configurations, and shows
required pins and pin usage. Refer to the device datasheet to see which actual I/O ports are used as EBI PORT0-3 for a
specific AVR XMEGA device.
EBI
SDRAM
WE
CAS/RE
RAS
DQM
CLK
CKE
BA[1:0]
Pxn
D[3:0]
A[7:0]]
WE
CAS
RAS
DQM
CLK
CKE
CS
BA[1:0]
A[7:0]
D[3:0]
A[11:8]
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相關(guān)代理商/技術(shù)參數(shù) |
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| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
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