參數(shù)資料
型號: MR80C32-25SBR
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù): 61/80頁
文件大?。?/td> 5152K
代理商: MR80C32-25SBR
261
XMEGA A [MANUAL]
8077I–AVR–11/2012
23.5.5 INTCTRL
Interrupt Control register
Bit 7:2
Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 1:0
INTLVL[1:0]: Interrupt priority and enable
These bits enable the AES interrupt and select the interrupt level, as described in “Interrupts and Programmable
Multilevel Interrupt Controller” on page 125. The enabled interrupt will be triggered when the SRIF in the STATUS
register is set.
Bit
7
654
32
1
0
+0x04
INTLVL[1:0]
Read/Write
R
R/W
Initial Value
0
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