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| 型號(hào)： | MR80C32-25SBR |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁(yè)數(shù)： | 6/80頁(yè) |
| 文件大?。?/td> | 5152K |
| 代理商： | MR80C32-25SBR |
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198
2466T–AVR–07/10
ATmega16(L)
Figure 93. Formats and States in the Slave Transmitter Mode
Miscellaneous States
There are two status codes that do not correspond to a defined TWI state, see Table 78.
Status $F8 indicates that no relevant information is available because the TWINT Flag is not set.
This occurs between other states, and when the TWI is not involved in a serial transfer.
Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
S
SLA
R
A
DATA
A
$A8
$B8
A
$B0
Reception of the own
slave address and one or
more data bytes
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
Arbitration lost as master
and addressed as slave
n
From master to slave
From slave to master
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-wire Serial Bus. The
prescaler bits are zero or masked to zero
P or S
DATA
$C0
DATA
A
$C8
P or S
All 1's
A
Table 78. Miscellaneous States
Status Code
(TWSR)
Prescaler Bits
are 0
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
Application Software Response
Next Action Taken by TWI Hardware
To/from TWDR
To TWCR
STA
STO
TWINT
TWEA
$F8
No relevant state information
available; TWINT = “0”
No TWDR action
No TWCR action
Wait or proceed current transfer
$00
Bus error due to an illegal
START or STOP condition
No TWDR action
0
1
X
Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
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