參數(shù)資料
型號(hào)： MR80C32-25SBR
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù)： 67/80頁
文件大小： 5152K
代理商： MR80C32-25SBR
267
XMEGA A [MANUAL]
8077I–AVR–11/2012
the EBI. The available configurations is shown in “Multiplexing Data with Address Byte 0” on page 267 through
Timing and Address Latch requirements is as for SRAM configuration.
24.6.1 Multiplexing Data with Address Byte 0
When the data byte and address byte 0 (AD[7:0]) are multiplexed, they are output from the same port, and the ALE1
signal from the device controls the address latch.
Figure 24-7. Multiplexed SRAM LPC connection using ALE1.
24.6.2 Multiplexing Data with Address Byte 0 and 1
When the data byte and address byte 0 (AD[7:0]), and address byte 1 (A[15:8]) are multiplexed, they are output from the
same port, and the ALE1 and ALE2 signal from the device control the external address latches.
Figure 24-8. Multiplexed SRAM LPC connection using ALE1 and ALE2.
24.7
SDRAM Configuration
Chip Select 3 on the EBI can be configured from SDRAM operation, and the EBI must be configured as a three-port or
four-port interface. The SDRAM can be configured for 4-bit or 8-bit data bus, and four-Port interface must be used for 8-
bit data bus. The SDRAM interface signals from the EBI to the SDRAM is listed in Table 24-2 on page 268.
EBI
SRAM
AD[7:0]
ALE1
D
Q
G
D[7:0]
A[7:0]
A[15:8]
A[19:16]
A[15:8]
EBI
SRAM
A[15:8]/
AD[7:0]
ALE1
ALE2
D
Q
G
D
Q
G
D[7:0]
A[7:0]
A[15:8]
A[19:16]
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