參數(shù)資料
型號(hào)： MR80C32-25SBR
廠商： TEMIC SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)： 76/80頁(yè)
文件大?。?/td> 5152K
代理商： MR80C32-25SBR
276
XMEGA A [MANUAL]
8077I–AVR–11/2012
Table 24-16. SDRAM row to precharge delay settings.
24.9.6 SDRAMCTRLC – SDRAM Control register C
Bit 7:6 – WRDLY[1:0]: SDRAM Write Recovery Delay
These bits select the write recovery time in number of ClkPER2 cycles, according to Table 24-17.
Table 24-17. SDRAM write recovery delay settings.
Bit 5:3 – ESRDLY[2:0]: SDRAM Exit Self-refresh to Active Delay
This field defines the delay between CKE set high and an ACTIVE command in a number of ClkPER2 cycles, according to
Table 24-18. SDRAM exit self-refresh delay settings.
RPDLY[2:0]
Group Configuration
Description
000
0CLK
Zero ClkPER2 cycles delay
001
1CLK
One ClkPER2 cycles delay
010
2CLK
Two ClkPER2 cycles delay
011
3CLK
Three ClkPER2 cycles delay
100
4CLK
Four ClkPER2 cycles delay
101
5CLK
Five ClkPER2 cycles delay
110
6CLK
Six ClkPER2 cycles delay
111
7CLK
Seven ClkPER2 cycles delay
Bit
7654
3
2
1
0
+0x09
WRDLY[1:0]
ESRDLY[1:0]
ROWCOLDLY[1:0]
Read/Write
R/W
Initial Value
0000
0
WRDLY[1:0]
Group configuration
Description
00
0CLK
Zero ClkPER2 cycles delay
01
1CLK
One ClkPER2 cycles delay
10
2CLK
Two ClkPER2 cycles delay
11
3CLK
Three ClkPER2 cycles delay
ESRDLY[2:0]
Group configuration
Description
000
0CLK
Zero ClkPER2 cycles delay
001
1CLK
One ClkPER2 cycles delay
010
2CLK
Two ClkPER2 cycles delay
011
3CLK
Three ClkPER2 cycles delay
100
4CLK
Four ClkPER2 cycles delay
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