參數(shù)資料
型號： MT90500
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）)
中文描述： 多通道自動柜員機(jī)AAL1特區(qū)（多通道自動柜員機(jī)AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口））
文件頁數(shù)： 108/159頁
文件大?。?/td> 514K
代理商： MT90500
MT90500
108
Table 64 - Event Count Register
Address: 60A2 (Hex)
Label: EVCR
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
Event_Cnt
15:0
R/O
This register keeps a running count of the reception of timing reference cells or 8 kHz
markers (as determined by setting of Cell / 8 kHz bit in register 60A0h). The contents of
this register are locked when a ‘1’ is written to the CNTUPDATE bit in the Clock Module
General Control Register (6080h). Thus CNTUPDATE should be set just prior to reading
this register. See Figure 31, “Adaptive Clock Recovery Sub-Module (Simplified Functional
Block Diagram),” on page 70 for more details.
Table 65 - CLKx1 Count - Low Register
Address: 60A4 (Hex)
Label: C1CRL
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
CLKx1_Cnt_L
15:0
R/O
This register represents the low portion of a 24-bit counter which keeps a running count of
CLKx1 * 8 periods (i.e. every 8 cycles of CLKx1, a counter is incremented). The counter is
updated at the same time the Event Count Register (60A2h) is incremented. The contents
of this register are locked when a ‘1’ is written to the CNTUPDATE bit in the Clock Module
General Control Register (6080h). This should be done just prior to reading this register.
See Figure 31, “Adaptive Clock Recovery Sub-Module (Simplified Functional Block
Diagram),” on page 70 for more details.
Table 66 - CLKx1 Count - High Register
Address: 60A6 (Hex)
Label: C1CRH
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
CLKx1_Cnt_H
7:0
R/O
This register represents the high portion of a 24-bit counter which keeps a running count of
CLKx1 * 8 periods (i.e. every 8 cycles of CLKx1, a counter is incremented). The counter is
updated at the same time the Event Count Register (60A2h) is incremented. The contents
of this register are locked when a ‘1’ is written to the CNTUPDATE bit in the Clock Module
General Control Register (6080h). This should be done just prior to reading this register.
See Figure 31, “Adaptive Clock Recovery Sub-Module (Simplified Functional Block
Diagram),” on page 70 for more details.
Reserved
15:8
R/O
Unused. Always read 00h.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90500AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
MT90502 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502AG 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
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