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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠(chǎng)商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線(xiàn)的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū)（多通道自動(dòng)柜員機(jī)AAL1分段及重組設(shè)備（基于通訊總線(xiàn)的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口）） |
| 文件頁(yè)數(shù)： | 84/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
84
5.2
Register Description
5.2.1
Microprocessor Interface Registers
Table 12 - Main Control Register
Address: 0000 (Hex)
Label: MCR
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
TDM_INTE
0
R/W
TDM Module Interrupt Enable. Enables interrupts from the TDM module when ‘1’. See
TDM_SERV in Register 0002h.
TX_SAR_INTE
1
R/W
TX_SAR Module Interrupt Enable. Enables interrupts from the TX_SAR module when ‘1’.
See TX_SAR_SERV in Register 0002h.
RX_SAR_INTE
2
R/W
RX_SAR Module Interrupt Enable. Enables interrupts from the RX_SAR module when ‘1’.
See RX_SAR_SERV in Register 0002h.
MUX_INTE
3
R/W
UTOPIA MUX Sub-module Interrupt Enable. Enables interrupts from the UTOPIA module
when ‘1’. See MUX_SERV in Register 0002h.
TIM_INTE
4
R/W
Timing Recovery Module Interrupt Enable. Enables interrupts from the Timing Recovery
module when ‘1’. See TIM_SERV in Register 0002h.
Reserved
10:5
R/W
Reserved. Must be set to “100_000”.
PAGE_MODE
11
R/W
For normal operation, set this bit to ‘1’.
PTXCLK_SEL
13:12
R/W
PTXCLK Select. Choose how PTXCLK is generated. “00”= PTXCLK pin is tristated
(external oscillator drives the pin); “01”= MCLK/2; “10”= MCLK/4; “11”=STXCLK.
CLOCKMOD
14
R/W
Clock Mode. When ‘0’, all external clocks (except MCLK) are replaced by MCLK/4. When
‘1’, all clocks operate normally. This feature ensures that all internal blocks in the MT90500
are reset even if some secondary clocks are absent. To prevent internal clock glitches, this
bit should be set before SRES is de-asserted.
SRES
15
R/W
Software Reset. When ‘0’, all modules except the CPU module are maintained in a reset
state. Note that the MT90500 is synchronously reset, and that MCLK should be applied
during reset. Reset should last at least 2
μ
sec when MCLK is 60 MHz (>75 clock cycles).
Note: SRES should be written to ‘1’ before any other register is accessed.
Table 13 - Main Status Register
Address: 0002 (Hex)
Label: MSR
Reset Value: 00X0 (Hex)
Label
Bit Position
Type
Description
TDM_SERV
0
R/O
TDM Module Service Request. When ‘1’, indicates the TDM module requires service (i.e.
at least one TDM Interface event bit (in register 6002h) and matching enable bit (in register
6000h) are set). When this bit is ‘1’ and the TDM_INTE interrupt enable bit is ‘1’ in the
MCR (Register 0000h), an external hardware interrupt is generated.
TX_SAR_SERV
1
R/O
TX_SAR Module Service Request. When ‘1’, indicates the TX_SAR module requires
service (i.e. at least one TX_SAR event bit (in register 2002h) and matching enable bit (in
register 2000h) are set). When this bit is ‘1’ and the TX_SAR_INTE interrupt enable bit is
‘1’ in the MCR (Register 0000h), an external hardware interrupt is generated.
RX_SAR_SERV
2
R/O
RX_SAR Module Service Request. When ‘1’, indicates the RX_SAR module requires
service (i.e. at least one RX_SAR event bit (in register 3002h) and matching enable bit (in
register 3000h) are set). When this bit is ‘1’ and the RX_SAR_INTE interrupt enable bit is
‘1’ in the MCR (Register 0000h), an external hardware interrupt is generated.
MUX_SERV
3
R/O
UTOPIA MUX Sub-module Service Request. When ‘1’, indicates the UTOPIA MUX sub-
module requires service (i.e. at least one UTOPIA event bit (in register 4002h) and
matching enable bit (in register 4000h) are set). When this bit is ‘1’ and the MUX_INTE
interrupt enable bit is ‘1’ in the MCR (Register 0000h), an external hardware interrupt is
generated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500 | Multi-Channel ATM AAL1 SAR |
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線(xiàn)的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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