參數(shù)資料
型號(hào)： MT90500
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）)
中文描述： 多通道自動(dòng)柜員機(jī)AAL1特區(qū)（多通道自動(dòng)柜員機(jī)AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口））
文件頁數(shù)： 73/159頁
文件大小： 514K
代理商： MT90500
MT90500
73
A 4-bit RTS value is generated once every “period of the RTS” (T
N
). Since one RTS value is carried by the CSI
bits in each 8-cell sequence, the “period of the RTS” is the assembly time of 8 cells on the designated SRTS
VC. The SRTS Transmit Byte Counter Register at 60B2h contains the number of payload bytes within an 8-cell
sequence of the SRTS VC. The value in this register is used to divide the byte frequency f
B
to obtain the
“period of the RTS”. For pointerless AAL1 Structured Data Transfer, the number of bytes necessary to fill 8 cells
is 376 (8 cells @ 47 bytes per cell). In Nx64 AAL1 SDT, the number of bytes required to fill 8 cells varies
depending on the number of P-bytes sent within an 8-cell sequence, but it is generally set to 375 bytes (1 cell
of 46 TDM payload bytes plus 7 cells of 47 TDM payload bytes). The SRTS Transmit Divider Register shown in
Figure 33 generates a latch pulse which captures the value of a free-running counter clocked by the external
signal fnx (the network reference clock, input at the FNXI pin). The latched value is the four-bit residual time
stamp. Multiple latches (a 5-deep FIFO) are used to synchronize this clocking block with cell transmission
(controlled by the transmit event schedulers).
In order for the SRTS clock recovery method to operate correctly, the divided-down network clock, FNXI, must
be properly derived. As stated in I.363.1:
“For SDH and non-SDH physical layers, a clock at frequency f
8
= 8 kHz, synchronized to a common
network clock, is available from which clocks at frequencies
f
nx
= f
8
x (19440 / 2
k
) kHz, where k = 0,1,2,...,12
can be derived. This set of derived frequencies can accommodate all service rates from 64 kbps up to
the full capacity of the STM-1 payload. The exact value of f
nx
to be used is uniquely specified since the
frequency ratio is constrained by 1
≤
f
nx
/f
s
< 2.”
For example, to support N = 24 (f
S
= 1.536 MHz) or N = 32 (f
S
= 2.048 MHz), the derived network frequency will
be 2.430 MHz (8000 * 19440 / 2
6
). To support N = 1 (f
S
= 64 kbps), the derived network frequency will be
75.9375 kHz (8000 * 19440 / 2
11
).
In compliance with I.363.1, the MT90500 transmits the 4-bit RTS values in the serial bit stream provided by the
CSI bits of successive odd-sequence-numbered SAR-PDU headers (the even-numbered CSI bits are available
for other uses such as SDT pointers). The modulo-8 sequence count provides a frame structure over 8 bits in
this serial bit stream. The MSB of the RTS is placed in the CSI bit of the SAR-PDU header with a sequence
count of 1.
Due to the internal hardware design of the MT90500, the frequency of FNXI must be < MCLK / 3. This places
no restrictions on the SRTS VC as long as MCLK is greater than 30 MHz. Since the maximum structure size is
122 channels, the maximum value of f
S
= 7.808 MHz, and the maximum value of f
nx
is 9.72 MHz.
4
ATM Physical Layer
Network Clock
Divide by x
4-bit counter
f
nx
RTS
4
MULTIPLE
LATCHES
clk
data_in
TX_SAR
BLOCK
FNXI
enable
Byte Counter
CLKx1
period of the RTS
(one 8-cell cycle)
f
B
Gapping Control
f
B
Generator
SRTS Transmit Divider Register
f
B
= f
S
/ 8 = service byte clock
Internal to MT90500
Transmit
ATM Cells
w/ CSI b
its
Figure 33 - Transmit SRTS Operation
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90500AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
MT90502 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502AG 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
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