參數(shù)資料
型號(hào)： PCI9060ES
廠商： Electronic Theatre Controls, Inc.
英文描述： 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
中文描述： 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng)
文件頁(yè)數(shù)： 17/192頁(yè)
文件大小： 1551K
代理商： PCI9060ES
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)
SECTION 2
PCI 9080
BUS OPERATION
PLX Technology, Inc., 1997
Page 8
Version 1.02
With Direct Slave and DMA modes (PCI 9080 local as
master):
PCI 9080 generates wait states with WAITO#
Local processor generates wait states with READYi#
Use Table 4-39[21:18, 5:2], Table 4-62[5:2], and
Table 4-67[5:2] to program the number of wait states
2.2.3.1.2 Wait State—PCI Side
When the wait state occurs on the PCI side, Master
throttles IRDY# and Slave throttles TRDY#.
2.2.3.2 Burst Mode and Continuous Burst
Mode (Bterm “Burst Terminate” Mode)
Table 2-7. Burst and Bterm on the Local Side
Mode
Burst
Bterm
Result
Single Cycle
0
0
One ADS# per data (default)
Single Cycle
0
1
Still one ADS# per data
Burst-4
1
0
One ADS# per four data
(use this mode for i960)
Burst Forever
1
1
One ADS# per BTERM#
On the local side, BLAST# and BTERM# perform the
following:
If burst is enabled (Table 4-39[26,24] for non-DMA,
Table 4-62[8] and Table 4-67[8] for DMA), but Bterm
is disabled (Table 4-39[7], Table 4-62[7] and Table
4-67[7]), then PCI 9080 bursts four Lwords. BLAST#
is generated at the fourth Lword (LA[3:2]=11), new
ADS# at the first Lword (LA[3:2]=00) of the next
burst.
If BTERM# sampling is enabled and BTERM# is low,
PCI 9080 forces a new ADS#, but does not generate
a new BLAST#.
BTERM# input is only valid when the PCI 9080 is
the Master of the local bus (Direct Slave or DMA
modes).
BTERM# is generated by external logic. It is input to
the PCI 9080 (and i960) and used to tell the PCI
9080 (and i960) to break up a burst cycle.
BTERM# is used for example to signal memory
access is crossing the page boundary.
On the PCI side, burst is always enabled.
Note:
following:
If Bterm is disabled, the PCI 9080 performs the
In every case, it performs four transactions.
32 bit local bus—Burst up to four Lwords
16 bit local bus—Burst up to two Lwords
8 bit local bus—Burst up to one Lword
Note:
9080 internal register bit. BTERM# refers to the PCI
9080 external signal.
In the following sections, Bterm refers to PCI
2.2.3.2.1 Burst Mode
If bursting is enabled and BTERM# input is not enabled,
bursting can start on any boundary and continue up to
an address boundary, as described in Table 2-8. After
the data at the boundary is transferred, PCI 9080
generates a new address cycle (ADS#).
Table 2-8. Burst Mode
Bus Mode
Burst
C, J
32-bit bus—Four Lwords or up to a quad Lword
boundary (LA3, LA2 = 11)
C, J
16-bit bus—Four words or up to a quad word
boundary (LA2, LA1 = 11)
C, J
8-bit bus—Four bytes or up to a quad byte
boundary (LA1, LA0 = 11)
S
16-bit bus—Eight words or up to a quad Lword
boundary (LA3, LA2 = 11)
2.2.3.2.2 Continuous Burst Mode (Bterm “Burst
Terminate” Mode)
Bterm mode enables PCI 9080 to perform long bursts to
devices that can accept longer than four Lword bursts.
PCI 9080 generates one address cycle and continues to
burst data. If a device requires a new address cycle after
a certain address boundary, it can assert BTERM# input
to cause the PCI 9080 to generate a new address cycle.
BTERM# input acknowledges the current data transfer
and requests that a new address cycle be generated
(ADS#). The address will be for the next data transfer. If
Bterm mode is enabled, PCI 9080 asserts BLAST# only
if its FIFOs become FULL/EMPTY or if a transfer is
complete.
Note:
until the previously described conditions are met.
If BTERM# is asserted, BLAST# does not assert
相關(guān)PDF資料
PDF描述
PCI9060SD 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
PCI950PT PC Card Support
PCI9656-AC66BI Controller Miscellaneous - Datasheet Reference
PCIB40 PC(ISA)BUS I/O CARD
PCICLOCKGEN_R001 AMD Alchemy? Solutions Au1500? PCI Clock Generation?
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCI9060ESF 功能描述:數(shù)字總線開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
PCI9060ESREV1 制造商:PLX Technology 功能描述:
PCI9060SD 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
PCI9060SD-1AF 功能描述:數(shù)字總線開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
PCI9080 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*