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參數(shù)資料
| 型號： | PCI9060ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁數(shù)： | 45/192頁 |
| 文件大小： | 1551K |
| 代理商： | PCI9060ES |
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 36
Version 1.02
master abort and target abort interrupt bits in the PCI
Status configuration register.
Bits [26:24] of the Interrupt Control/Status Register (refer
to Table 4-58) are latched at the time of a target abort
interrupt or master abort interrupt. They provide
information as to who was master when an abort
occurred. PCI 9080 updates these bits whenever an
abort occurs.
3.12.2 Local Interrupts (LINTo#)
A PCI 9080 Local Interrupt (LINTo#) can be generated
by one of the following:
PCI to Local Doorbell/Mailboxes Register access
PCI BIST interrupt, the DMA done interrupt
DMA terminal count is reached
DMA abort interrupt or messaging outbound post
queue not empty
LINTo#, or individual sources of an interrupt, can be
enabled or disabled with the PCI 9080 Interrupt
Control/Status Register (refer to Table 4-58). Interrupt
Control/Status Register also provides interrupt status for
each source of the interrupt.
PCI 9080 local interrupt is a level output. An interrupt
can be cleared by disabling the interrupt enable bit of a
source or by clearing the cause of an interrupt.
3.12.2.1 Local to PCI Doorbell Interrupt
A local bus master can generate a PCI bus interrupt by
writing to the Local to PCI Doorbell Register (refer to
Table 4-57). PCI host processor can then read PCI 9080
Interrupt Control/Status Register (refer to Table 4-58) to
determine that a doorbell interrupt is pending. It can then
read the PCI 9080 Local to PCI Doorbell Register.
Each bit in the Local to PCI Doorbell Register is
individually controlled. Bits in the Doorbell Register can
only be set by the local side. From the local side, writing
a 1 to any bit position sets that bit and writing a 0 to a bit
position has no effect. Bits in the Local to PCI Doorbell
Register can only be cleared from the PCI side. From
the PCI side, writing a 1 to any bit position clears that bit
and writing a 0 to a bit position has no effect.
The interrupt remains asserted as long as any of the
Local to PCI Doorbell Register bits are set and PCI
Doorbell interrupt is enabled.
To prevent race conditions when the PCI bus is
accessing the Doorbell Register (or any configuration
register), PCI 9080 automatically de-asserts READYo#
to prevent local bus accesses.
3.12.2.2 PCI to Local Doorbell Interrupt
A PCI bus master can generate a local bus interrupt by
writing to the PCI to Local Doorbell Register (refer to
Table 4-56). Local processor can then read the PCI
9080 Interrupt Control/Status Register (refer to Table 4-
58) to determine that a doorbell interrupt is pending. It
can then read the PCI 9080 PCI to Local Doorbell
Register.
Each bit in the PCI to Local Doorbell Register is
individually controlled. Bits in the Doorbell Register can
only be set by the PCI side. From the PCI side, writing 1
to any bit position sets that bit and writing 0 to a bit
position has no effect. Bits in the PCI to Local Doorbell
Register can only be cleared from the local side. From
the local side, writing 1 to any bit position clears that bit
and writing 0 to a bit position has no effect.
Note:
not use the PCI to Local Doorbell Register.
If local side cannot clear Doorbell Interrupt, do
The interrupt remains asserted as long any of the PCI to
Local Doorbell Register bits are set and the Local
Doorbell interrupt is enabled.
To prevent race conditions when the local bus is
accessing the Doorbell Register (or any configuration
register), PCI 9080 automatically issues a RETRY to the
PCI bus.
3.12.2.3 Built-In Self Test Interrupt (BIST)
A PCI bus master can generate a local bus interrupt by
performing a PCI Type 0 configuration write to a bit in
the PCI BIST Register. The local processor can then
read the PCI 9080 Interrupt Control/Status Register
(refer to Table 4-58) to determine that a BIST interrupt is
pending.
The interrupt remains asserted as long as the bit is set
and the BIST interrupt is enabled. The local bus then
resets the bit when BIST is complete. PCI Host software
may fail the device if the bit is not reset after two
seconds.
Note:
PCI 9080 does not have internal BIST.
3.12.2.4 DMA Channel 0/1 Interrupts
A DMA channel can generate a PCI or local bus interrupt
when done (transfer complete) or after a transfer is
complete for a descriptor in chaining mode. A bit in the
DMA mode register determines whether to generate a
PCI or local interrupt. The local or PCI processor can
then read the PCI 9080 Interrupt Control/Status Register
(refer to Table 4-58) to determine whether a DMA
channel interrupt is pending.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI9060ESF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9060ESREV1 | 制造商:PLX Technology 功能描述: |
| PCI9060SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060SD-1AF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9080 | 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip |
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