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參數(shù)資料
| 型號： | PCI9060ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁數(shù)： | 30/192頁 |
| 文件大小： | 1551K |
| 代理商： | PCI9060ES |
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 21
Version 1.02
The register number (bits [7:2]) or device number
(bits [15:11]) must be modified and a new CFT
read/write cycle must be performed before other
registers or devices can be accessed.
3.6.1.7 Direct Bus Master Lock
PCI 9080 supports direct local to PCI bus exclusive
accesses (locked atomic operations). A locked operation
must start with the local bus input LLOCK# being
asserted during a Direct Master bus read cycle. Refer to
the timing in Section 8, “Timing Diagrams.”
3.6.1.8 Master/Target Abort
PCI 9080 Master/Target abort logic enables a local bus
master to perform a Direct Master bus poll of devices to
determine whether the devices exist (typically when the
local bus performs configuration cycles to the PCI bus).
If a PCI Master, Target Abort, or Retry Time-out is
encountered during a transfer, PCI 9080 asserts
LSERR# if enabled (refer to INTCSR[1:0], Table 4-58)
(can be used as an NMI). If the local bus master is
waiting for a READYo#, it is asserted along with
BTERMo#. The local master’s interrupt handler can take
the appropriate application specific action. It can then
clear the abort bits in the PCI Status configuration
register (refer to Table 4-12) of the PCI 9080 to clear the
LSERR# interrupt and re-enable Direct Master transfers.
If a local bus master is attempting a burst read from a
nonresponding PCI device (Master/Target abort), it
receives the READYo# and BTERMo# for the first cycle
only. If the local processor cannot terminate its burst
cycle, it may cause the local processor to hang. The
local bus must then be reset from the PCI bus or by a
local watchdog timer asserting RESETi#. If the local bus
master cannot terminate its cycle with BTERMo#, it
should not perform burst cycles when attempting to
determine whether a PCI device exists.
3.6.1.9 Write and Invalidate
PCI 9080 can be programmed to perform write and
invalidate cycles to the PCI for DMA and Direct Master
transfers. PCI 9080 supports Write and Invalidate
transfers for cache line sizes of 8 or 16 Lwords. The size
is specified in the PCI Cache Line Size Register. If a size
other than 8 or 16 is specified, PCI 9080 performs write
transfers rather than Write and Invalidate transfers.
3.6.1.9.1 DMA Write and Invalidate
DMA Write and Invalidate transfers are enabled when
the write and invalidate enable bit of a DMA controller is
set in its Mode Register and the Memory Write and
Invalidate enable bit is set in the PCI Command
Register.
In Write and Invalidate mode, PCI 9080 waits until the
number of Lwords required for the specified cache line
size have been read from the local bus before starting
the PCI access. This ensures that a complete cache line
write can be completed in one PCI bus ownership. If a
target disconnects before a cache line is completed, PCI
9080 completes the remainder of that cache line using
normal writes before resuming write and invalidate
transfers. If a write and invalidate cycle is in progress,
PCI 9080 continues to burst if another cache line has
been read from the local bus before the cycle completes.
Otherwise, PCI 9080 terminates the burst and waits for
the next cache line to be read from the local bus. If the
final transfer is not a complete cache line, PCI 9080
completes DMA transfer using normal writes.
3.6.1.9.2 Direct Master Write and Invalidate
Direct Master Write and Invalidate transfers are enabled
when the invalidate enable bit is set in the PCI Base
Address (Remap) Register for Direct Master to PCI
Memory and the Memory Write and Invalidate enable bit
is set in the PCI Command Register (refer to Table 4-
11).
In Write and Invalidate mode, if the start address of the
Direct Maser transfer is on a cache line boundary, PCI
9080 waits until the number of Lwords required for
specified cache line size have been written from the
local bus before starting PCI Write and Invalidate
access. This ensures that a complete cache line write
can be completed in one PCI bus ownership. If the start
address is not on a cache line boundary, PCI 9080 starts
a normal PCI write access. PCI 9080 terminates a cycle
at a cache line boundary if it is performing a normal write
or if it is performing a Write and Invalidate cycle and
another cache line of data is not available. If an entire
cache line is available by the time the PCI 9080 regains
use of the PCI bus, PCI 9080 resumes Write and
Invalidate cycles. Otherwise, it continues with a normal
write. If a target disconnects before a cache line is
completed, PCI 9080 completes the remainder of that
cache line using normal writes.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCI9060ESF | 功能描述:數(shù)字總線開關 IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關數(shù)量:24 傳播延遲時間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9060ESREV1 | 制造商:PLX Technology 功能描述: |
| PCI9060SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060SD-1AF | 功能描述:數(shù)字總線開關 IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關數(shù)量:24 傳播延遲時間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9080 | 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip |
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