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參數(shù)資料
| 型號： | PCI9060ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁數(shù)： | 50/192頁 |
| 文件大小： | 1551K |
| 代理商： | PCI9060ES |
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 41
Version 1.02
3.13.5 Inbound Post List FIFO
A PCI master (Host or another IOP) can write a
message into an available message frame in shared
local (IOP) memory. It can then post that message by
writing the message frame address (MFA) to the
Inbound Queue Port Address (40h of the first PCI
Memory Base Address Register). When the port is
written, the MU writes the MFA to the Inbound Post List
FIFO location pointed to by the Queue Base Register +
FIFO Size + Inbound Post Head Pointer Register. After
the MU writes the MFA to the Inbound Post List FIFO, it
increments the Inbound Post Head Pointer Register.
Inbound Post Tail Pointer Register points to the Inbound
Post List FIFO location which holds the MFA of the
oldest posted message. The tail pointer is maintained by
the local processor. After a local processor reads the
oldest MFA, it can remove the MFA from the Inbound
Post List FIFO by incrementing the Inbound Post Tail
Pointer Register.
PCI 9080 generates a local Interrupt when the Inbound
Post List FIFO is not empty. Inbound Post List FIFO
Interrupt bit in the Queue Status/Control Register (QSR)
indicates interrupt status. The interrupt clears when the
Inbound Post List FIFO is empty. The interrupt can be
masked by the Inbound Post List FIFO Interrupt Mask bit
(refer to Table 4-89[4]).
To prevent race conditions from the time the PCI write
transaction is received until the data is written in local
memory and the Inbound Post Head Pointer Register is
incremented, any PCI direct slave access to the PCI
9080 is issued a RETRY.
3.13.6 Outbound Post List FIFO
A local master (IOP) can write a message into an
available message frame in shared Host memory. It can
then post that message by writing the message frame
address (MFA) to the Outbound Post List FIFO location
pointed to by the Queue Base Register + Outbound Post
Head Pointer Register + (2 * FIFO Size). The local
processor should then increment the Outbound Post
Head Pointer Register.
A PCI master can obtain the MFA of the oldest posted
message by reading the Outbound Queue Port Address
(44h of the first PCI Memory Base Address Register). If
FIFO is empty (no more outbound messages are posted,
head and tail pointers are equal), the MU returns a value
of -1 (FFFFFFFFh). If Outbound Post List FIFO is not
empty (head and tail pointers are not equal), the MU
reads the MFA pointed to by the Queue Base Register +
(2 * FIFO Size) + outbound Post Tail Pointer Register,
returns its value and increments the Outbound Post Tail
Pointer Register.
PCI 9080 generates a PCI Interrupt when the Outbound
Post Head Pointer Register is not equal to the Outbound
Post Tail Pointer Register. Outbound Post List FIFO
Interrupt bit of the Outbound Post List FIFO Interrupt
Status (OPLFIS) Register indicates interrupt status.
When the pointers become equal, both the interrupt and
the Outbound Post List FIFO interrupt bit are
automatically cleared. The pointers become equal when
a PCI master (Host or another IOP) reads enough FIFO
entries to empty the FIFO. The interrupt can be masked
by the Outbound Post List FIFO Interrupt Mask
(OPLFIM) Register).
3.13.7 Outbound Post Queue
To reduce read latency, prefetching from the tail of the
queue occurs whenever the queue is not empty and the
tail pointer is incremented (queue has been read from),
or when the queue is empty and the head pointer is
incremented (queue has been written to). When the host
CPU reads the Outbound Post Queue, the data is
immediately available.
3.13.8 Inbound Free Queue
To reduce read latency, prefetching from the tail of the
queue occurs whenever the queue is not empty and the
tail pointer is incremented (queue has been read from),
or when the queue is empty and the head pointer is
incremented (queue has been written to). When the host
CPU reads the Inbound Free Queue, the data is
immediately available.
3.13.9 Outbound Free List FIFO
A PCI master (Host or another IOP) allocates outbound
message frames in its shared memory and can place the
address of a free (available) message frame into the
Outbound Free List FIFO by writing the message frame
address (MFA) to the Outbound Queue Port Address
(44h of the first PCI Memory Base Address Register).
When the port is written, the MU writes the MFA to the
Outbound Free List FIFO location pointed to by the
Queue Base Register + (3 * FIFO Size) + Outbound
Free Head Pointer Register. After the MU writes the
MFA to the Outbound Free List FIFO, it increments the
Outbound Free Head Pointer Register.
When the IOP needs a free outbound message frame, it
must first check whether any free frames are available. If
Outbound Free List FIFO is empty (outbound free head
and tail pointers are equal), the IOP must wait for the
Host to place additional outbound free message frames
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PCI9060ESF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9060ESREV1 | 制造商:PLX Technology 功能描述: |
| PCI9060SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060SD-1AF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9080 | 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip |
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