- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367822 > PCI9060SD (Electronic Theatre Controls, Inc.) 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS PDF資料下載
參數(shù)資料
| 型號： | PCI9060SD |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁數(shù)： | 42/192頁 |
| 文件大?。?/td> | 1551K |
| 代理商： | PCI9060SD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當(dāng)前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁
SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 33
Version 1.02
DREQ[1:0]# is de-asserted, the second Lword is not
transferred.
DREQ[1:0]# controls only the number of Lword transfers.
For an 8-bit bus, PCI 9080 gives up the bus after the last
byte for the Lword is transferred. For a 16-bit bus, PCI
9080 gives up the bus after the last word for the Lword is
transferred.
3.7.5 DMA Priority
DMA Channel 0 priority, DMA Channel 1 priority, or
rotating priority can be specified in the DMA Arbitration
Register.
3.7.6 DMA Arbitration
PCI 9080 DMA controller releases control of the local
bus (de-asserts LHOLD) when one of the following
occurs:
FIFOs are full in a local to PCI transfer
FIFOs are empty in a PCI to local transfer
Local Bus Latency Timer expires (if enabled)
BREQ input is asserted (BREQ can be enabled or
disabled, or gated with a latency timer before the
PCI 9080 gives up the local bus)
Direct Slave access is pending
EOT input is received (if enabled)
DMA controller releases control of the PCI bus when one
of the following occurs:
FIFOs are full or empty
PCI Latency Timer expires and loses the PCI grant
signal
Target Disconnect response received
DMA controller de-asserts its PCI bus request (REQ#)
for a minimum of two PCI clocks.
3.7.6.1 End of Transfer (EOT0# or EOT1#)
Input
DMA Mode Register bit 14 (BLAST mode for EOT),
determines the number of Lwords transferred after a
DMA controller EOT[1:0]# input is asserted.
If BLAST# output is not required for the last Lword of the
DMA transfer (bit 14 = 1), the DMA controller releases
the data bus and terminates DMA after it receives an
external READYi# or the internal wait state counter
decrements to a value of 0 for the current Lword. If the
DMA controller is currently bursting data, which is not
the last data phase for the burst, BLAST# output will not
be asserted.
If BLAST# output is required for the last Lword of the
DMA transfer (bit 14 = 0), the DMA controller transfers
one or two Lwords. If EOT[1:0]# is asserted, the DMA
controller completes the current Lword, and one
additional Lword (this allows BLAST# output to be
asserted during the final Lword). If DMA FIFO is
full/empty after the data phase in which EOT[1:0]# is
asserted, the second Lword is not transferred.
DMA controller terminates a transfer on an Lword
boundary after EOT[1:0]# is asserted. For an 8-bit bus,
PCI 9080 terminates after the last byte for the Lword is
transferred. For a 16-bit bus, PCI 9080 terminates after
the last word for the Lword is transferred.
3.7.6.2 DMA Abort
A DMA transfer can be aborted. The abort process is as
follows:
1.
DMA Channel must be enabled (Table 4-72[0]=1).
2.
DMA Channel must be started (Table 4-72[1]=1).
3.
Wait for the Channel Done bit to be set to zero
(Table 4-72[4]=0).
4.
Disable the DMA Channel (Table 4-72[0] =0).
5.
Abort DMA by programming the Channel Abort bit
(Table 4-72[2]=1).
6.
Wait until the Channel Done bit is set (Table 4-
72[4]=1).
Note:
One to two data transfers occur after the abort
bit is set. Aborting when no DMA cycles are in progress
causes the next DMA to abort.
3.7.6.3 Local Latency and Pause Timers
A Local Bus Latency Timer and Local Bus Pause Timer
are programmable with the DMA Arbitration Register. If
local latency timer expires, PCI 9080 completes the
current Lword transfer and releases LHOLD. After its
programmable Pause Timer expires, it reasserts
LHOLD. When it receives LHOLDA, it continues the
transfer. PCI bus transfer continues until the FIFO is
empty for a local to PCI transfer or until it is full for a PCI
to local transfer.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI950PT | PC Card Support |
| PCI9656-AC66BI | Controller Miscellaneous - Datasheet Reference |
| PCIB40 | PC(ISA)BUS I/O CARD |
| PCICLOCKGEN_R001 | AMD Alchemy? Solutions Au1500? PCI Clock Generation? |
| PCK2000 | CK97 (66/100MHz) System Clock Generator(CK97 (66/100MHz) 系統(tǒng)時鐘發(fā)生器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI9060SD-1AF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9080 | 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip |
| PCI9080 REV3 | 制造商:PLX TECH 功能描述: |
| PCI9080-3 | 功能描述:外圍驅(qū)動器與原件 - PCI I2O Compatible PCI BUS MASTER I/O CHIP RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI9080-3 G | 功能描述:外圍驅(qū)動器與原件 - PCI 32Bit Master Chip RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。