
Data Sheet
23
Rev. 1.0, 2005-06-02
OctalLIU
TM
PEF 22508 E
Pin Descriptions
A13
RL1.7
I (analog) –
Line Receiver input 1, port 7
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
ROID7
I
–
Receive Optical Interface Data, port 7
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). If CMI coding is
selected (MR0.RC(1:0) = 01
b and LIM0.DRS = 1), an
internal DPLL recovers clock an data; no clock signal on
RCLKI2 is required.
A15
RL2.7
I (analog) –
Line Receiver input 2, port 7
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
A14
RLS27
IO
(analog)
–
Receive Line Switch, port 7
Connector of the analog switch.
A11
RL1.8
I (analog) –
Line Receiver input 1, port 8
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
ROID8
I
–
Receive Optical Interface Data, port 8
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). If CMI coding is
selected (MR0.RC(1:0) = 01
b and LIM0.DRS = 1), an
internal DPLL recovers clock an data; no clock signal on
RCLKI2 is required.
A10
RL2.8
I (analog) –
Line Receiver input 2, port 8
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
B10
RLS28
IO
(analog)
–
Receive Line Switch, port 8
Connector of the analog switch.
Line Interface Transmitter
D7
XL1.1
O
(analog)
–
Transmit Line 1, port 1
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
XOID1
O
–
Transmit Optical Interface Data, port 1
Data in CMI code is shifted out with 50% or 100% duty
cycle on both transitions of XCLK2 according to the CMI
coding. Output polarity is selected by bit LIM0.XDOS
(after reset: data is sent active high). The single-rail
mode is selected if LIM1.DRS is set and MR0.XC1 is
cleared. After reset this pin is in high-impedance state
until register LIM1.DRS is set and XPM2.XLT is cleared.
D6
XL2.1
O
(analog)
–
Transmit Line 2, port 1
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Table 1
I/O Signals (cont’d)
Pin No. Ball
No.
Name
Pin Type Buffer
Type
Function