
OctalLIU
TM
PEF 22508 E
Functional Description
Data Sheet
44
Rev. 1.0, 2005-06-02
n: even address
3.5.2
Serial Micro Controller Interfaces
Two serial interfaces are included to enable device programming and controlling:- Slave Serial Control Interface
(SCI) - Slave Serial Peripheral Interface (SPI)
By using the SCI Interface, the OctalLIU
TM can be easily connected to Infineon interworking devices plus Infineon
SHDSL- and ADSL-PHYs so that implementation of different line transmission technologies on the same line card
easily is possible. The SCI interface is a three-wire bus and optionally replaces the parallel processor interface to
reduce wiring overhead on the PCB, especially if multiple devices are used on a single board. Data on the bus is
HDLC encapsulated and uses a message-based communication protocol.
If SCI interface with multipoint to multipoint configuration is used, address pins A(5:0) are used for SCI source
(slave) address pin strapping, see Table 2.
Note that after a reset writing into or reading from OctalLIU
TM registers using the SCI- or SPI-Interface is not
possible until the PLL is locked: If the SCI-Interface is used no acknowledge message will be sent by the
OctalLIU
TM. If the SPI-Interface is used pin SDO has high impedance (SDO is pulled up by external resistor). To
trace if the SPI interface is accessible, the micro controller should poll for example the register DSTR so long as
it read no longer the value F
H .
3.5.2.1
SCI Interface
The Serial Control Interface (SCI) is selected if IM(1:0) is strapped to 11
H.
The OctalLIU
TM SCI interface is always a slave.
Figure 49 shows the timing diagram of the SCI interface, Table 56 gives the appropriate values of the timing
parameters.
Figure 6 shows a first application using the SCI interfaces of some OctalLIU
TMs where point to point full duplex
connections are realized between every OctalLIU
TM and the micro controller. Here the data out pins of the SCI
interfaces (SCI_TXD) of the OctalLIU
TMs must be configured as push-pull (PP), see configuration register bit PP
Figure 7 shows an application with Multipoint to multipoint connections between the OctalLIU
TMs and the micro
controller (half duplex). Here the data out pin of the SCI interfaces (SCI_TXD) of all OctalLIU
TMs must be
configured as an open Drain (oD), see configuration register bit PP in Table 8. The data out and data in pins
(SCI_RXD, SCI_TXD) of each OctalLIU
TM are connected together to form a common data line. Together with a
common pull up resistor for the data line, all open Drain data out pins are building a wired And.
The Infineon proprietary Daisy-Chain approach is not supported
The group address of the SCI interface is 00
H after reset. Recommendation for configuring is C4H to be different
to the group addresses of all other Infineon devices.
In case of multipoint to multipoint applications the 6 MSBs of the SCI source address will be defined by
pinstrapping of the address pins A5 to A0. The two LSBs of the SCI source address are constant 10B, see
Table 8. The SCI source address can be overwritten by a write command into the SCI configuration register. For
applications with point to point connections for the SCI interface the source address is not valid.
Because 14 bits are used for the register addresses in the SCI interface macro the two MSBs of the 16 bit wide
register addresses are set fixed to zero.
Intel
(Address n + 1)
(Address n)
Motorola
(Address n)
(Address n + 1)
↑
↓
Data lines
D15
D8
D7
D0