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參數(shù)資料
| 型號(hào)： | PEF22508E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, LBGA-256 |
| 文件頁數(shù)： | 95/193頁 |
| 文件大?。?/td> | 10683K |
| 代理商： | PEF22508E |
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OctalLIU
TM
PEF 22508 E
Operational Description
Data Sheet
184
Rev. 1.0, 2005-06-02
must be programmed before the activation procedure of the PCM line starts. Such procedures are specified in
ITU-T recommendations (e.g. fault conditions and consequent actions). Setting optional parameters primarily
makes sense when basic operation via the PCM line is guaranteed. Table 71 gives an overview of the most
important parameters in terms of signals and control bits which are to be programmed in one of the above steps.
The sequence is recommended but not mandatory. Accordingly, parameters for the basic and operational set up,
for example, can be programmed simultaneously. The bit MR1.PMOD must always be kept high (otherwise E1
mode is selected). J1 mode is selected by additionally setting RC0.SJR = 1.
Features like channel loop-back, idle channel activation, clear channel activation, extensions for signaling support,
alarm simulation, etc. are activated later. Transmission of alarms (e.g. AIS, remote alarm) and control of
synchronization in connection with consequent actions to remote end and internal system depend on the activation
procedure selected.
Note: Read access to unused register addresses: value should be ignored. Write access to unused register
addresses: should be avoided, or set to 00
H. All control registers (except XS(12:1), CMDR, DEC) are of
type read/write
Specific T1/J1 Configuration
The following is a suggestion for a basic configuration to meet most of the T1/J1 requirements. Depending on
different applications and requirements any other configuration can be used.
Table 71
Configuration Parameters (T1/J1)
Basic Set Up
T1
J1
Master clocking mode
GCM(6:1) according to external MCLK clock frequency
T1/J1 mode select
MR1.PMOD = 1,
Clock system configuration
CMR(3:1), GPC1; if COMP = 0 CMR(6:4) and GPC(6:2)
Specification of line interface
LIM0, LIM1,
Specification of transmit pulse mask XPM(2:0) or TXP(16:1)
Line interface coding
MR0.XC(1:0), MR0.RC(1:0)
Loss-of-signal detection/recovery
conditions
PCD, PCR, LIM1, LIM2
AIS to framer interface
MR2.XAIS
Multi Function Port selection
PC(3:1)
Table 72
Line Interface Configuration (T1/J1)
Register
Function
MR2.DAIS = 1
Disables AIS insertion into the data stream (necessary for proper operation)
LOOP.RTM = 1
Sets the receive dual elastic store in a “free running” mode (necessary for proper
operation)
MR4.TM = 1
Enables transparent mode (necessary for proper operation)
MR5.XTM = 1
Sets the transmitter in a “free running” mode (necessary for proper operation)
CCB(3:1) = FF
H‘
“Clear Channel” mode is selected (necessary for proper operation only if AMI code is
selected)
MR0.XC0/1
MR0.RC0/1
LIM1.DRS
CCB(3:1)
DIC3.CMI
The OctalLIU
TM supports requirements for the analog line interface as well as the
digital line interface. For the analog line interface the codes AMI (with and without bit
7stuffing) and B8ZS are supported. For the digital line interface modes (dual- or
single-rail) the OctalLIU
TM supports AMI (with and without bit 7 stuffing), B8ZS (with
and without B8ZS precoding).
PCD = 0A
H
LOS detection after 176 consecutive “zeros” (fulfills G.775/Telcordia (Bellcore)/AT&T)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEF22508EV1.1-G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| PEF22508EV11G | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
| PEF22508EV11GXP | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22508EV11GXT | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22509EV1.1 | 制造商:Infineon Technologies AG 功能描述:SP000205605_T/E ASIC_TY_PB |
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