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OctalLIU
TM
PEF 22508 E
Functional Description
Data Sheet
46
Rev. 1.0, 2005-06-02
Figure 8
SCI Message Structure of OctalLIU
TM
Every write into or read from a register of the OctalLIU
TM is initiated by a command message CMD from the Host
(micro con roller) and is then confirmed by an acknowledge message ACK from the OctalLIU
TM if in the SCI
configuration automatic acknowledgement is set (bit ACK_EN, see Table 8).
The frame structure of this messages are shown in Figure 9.
In general the LSB of every byte is transmitted first and lower bytes are transmitted before higher bytes (regarding
the register address)
Source and destination addresses are 8 bits long. Only the first 6 bits are really used for addressing. The bit C/R
(Command/Response) distinguishes between a command and a response. The bit MS (Master/Slave) is 0
B for
all Slaves and 1
The source address is defined by pinstrapping of A5 to A0 after reset, but other values can be configured by
programming of the SCI configuration register.
The payload of the write CMD includes two control bits (MSBs of the payload), which distinguish between the
different kind of commands, see Table 7, the 14 bit wide register address and the 8 bit wide data whereas the read
CMD payload includes only the control bits and the register address. Register addresses can be either OctalLIU
TM
register addresses or SCI configuration register addresses. Because of the address space of the OctalLIU
TM,
really 11 LSBs of the 14 bit address are used in the OctalLIU
TM. The 3 MSBs are ignored
The Frame Check Sequence FCS has16 bits
The Read Status Byte RSTA of the acknowledge message shows the status of the received message and is built
by the SCI interface of the OctalLIU
The destination address in the ACK message is always the source address of the corresponding CMD (the
address of the micro controller), see Figure 10, because no CMD messages will be sent by the OctalLIU
TM SCI
interface
HOST
OctalLIU
CMD
ACK
OctalLIU_SCI_message_structure