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參數(shù)資料
| 型號(hào)： | PEF22508E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, LBGA-256 |
| 文件頁(yè)數(shù)： | 165/193頁(yè) |
| 文件大?。?/td> | 10683K |
| 代理商： | PEF22508E |
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Data Sheet
73
Rev. 1.0, 2005-06-02
OctalLIU
TM
PEF 22508 E
Functional Description
to TCLK is automatically performed if CMR6.ATCS = 1. All switchings of XCLK between TCLK and the DCO-
X output are shown in the interrupt status bit ISR7.XCLKSS0 which is masked by IMR7.XCLKSS0. These
kinds of switching cannot be done in general without causing phase jumps in the transmit clock XCLK.
Additionally after loss of TCLK the transmit clock XCLK is also lost during the “detection time” for loss of TCLK
and the transmit pulses are disturbed. If CMR6.ATCS is cleared, TCLK is used (again) as source for the
transmit clock XCLK, independent if TCLK is lost or not. The interrupt status bit ISR7.XCLKSS0 will be set also.
If the transmit clock XCLK is sourced by the DCO-X output and the DCO-X reference clock is TCLK, the DCO-
X reference will be switched automatically (if CMR6.ATCS = 1) to FCLKX (see multiplexer “F” in Figure 29)
after a loss of TCLK was detected. If the DCO-X reference was switched to FCLKX and TCLK becomes active,
switching of the reference (back) to TCLK is automatically performed if CMR6.ATCS = 1. All switchings of the
reference between TCLK and FCLKX are shown in the interrupt status bit ISR7.XCLKSS1 which is masked by
IMR7.XCLKSS1. For these kinds of automatically switching, the transmit clock XCLK fulfills the jitter-, wander-
and frequency deviation- requirements as specified for E1/T1 after the clock source of the DCO-X was
changed. If CMR6.ATCS is cleared, TCLK is used (again) as reference for the DCO-X, independent if TCLK
is lost or not. The interrupt status bit ISR7.XCLKSS1 will be set also.
The status register bits CLKSTAT.TCLKLOS and CLKSTAT.FCLKXLOS (CLKSTAT) show if the appropriate
clock is actual lost or not, so together with ISR7.XCLKSS1 and ISR7.XCLKSS0 the complete information
regarding the current status of the transmit clock system is provided.
3.9.4
Transmit Jitter Attenuator
The transmit jitter attenuator is based on the so called DCO-X (digital clock oscillator, transmit) in the transmit path.
Jitter attenuation of the transmit data is done in the transmit elastic buffer, see Figure 29. The DCO-X circuitry
generates a "jitter-free" transmit clock and meets the E1 requirements of ITU-T I.431, G. 736 to 739, G.823 and
ETSI TBR12/13 and the T1 requirements of AT&T PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253, TR-
TSY 499 and ITU-T I.431, G.703 and G. 824. The DCO-X circuitry works internally with the same high frequency
clock as the DCO-R. It synchronizes either to the working clock of the transmit system interface (internal transmit
clock) or the clock provided on multi function pin TCLK or the receive clock RCLK (remote loop/loop-timed). The
DCO-X attenuates the incoming jitter starting at its corner frequency with 20 dB per decade fall-off. With the jitter
attenuated clock, which is directly depending on the phase difference of the incoming clock and the jitter
attenuated clock, data is read from the transmit elastic buffer (512/386 bit) or from the JATT buffer (512/386 bit,
remote loop), see Figure 31. Wander with a jitter frequency below the corner frequency is passed transparently.
The dual transmit elastic buffer can buffer two data streams so that dual rail mode is possible at the transmit framer
interface (XDIP/XDIN).
The DCO-X is equivalent to the DCO-R so that the principle for its configuring is the same, see Figure 23 and
The DCO-X reference clock is monitored: If one, two or three clock periods of the 2.048 MHz (1.544 MHz in T1/J1
mode) clock at FCLKX are missing the DCO-X regulates its output frequency. If four or more clock periods are
missing
The DCO-X circuitry is automatically centered to the nominal frequency of 2.048 MHz (1.544 MHz in T1/J1) if
the center function of DCO-X is enabled by CMR2.DCOXC = 1.
The actual DCO-X output frequency is “frozen” if the center function of DCO-R is disabled by
CMR2.DCOXC = 0.
The jitter attenuated clock is output on pin XCLK if the transmit jitter attenuator is enabled, see multiplexer “H” in
The transmit jitter attenuator can be disabled. In that case data is read from the transmit elastic buffer with the
clock sourced on pin TCLK, see multiplexer “H” in Figure 29. Synchronization between FCLKX and TCLK has to
be done externally.
In the loop-timed clock configuration (LIM2.ELT) the DCO-X circuitry generates a transmit clock which is frequency
synchronized on RCLK, see Figure 31 and multiplexers “G” and “F” in Figure 29. In this configuration the transmit
elastic buffer has to be enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEF22508EV1.1-G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| PEF22508EV11G | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
| PEF22508EV11GXP | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22508EV11GXT | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
| PEF22509EV1.1 | 制造商:Infineon Technologies AG 功能描述:SP000205605_T/E ASIC_TY_PB |
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