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OctalLIU
TM
PEF 22508 E
Pin Descriptions
Data Sheet
30
Rev. 1.0, 2005-06-02
B1
RPA1
I/O
PU/–
Receive Multifunction Pins A to C, port 1
Depending on programming of bits PC(1:3).RPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the OctalLIU
TM. After
reset these ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESR
latching/transmission of data is done with the rising or
falling edge of FCLKR. If not connected, an internal pull-
up transistor ensures a high input level.
An input function must not be selected twice or more.
Selectable pin functions are described below.
D2
RPB1
I/O
PU/–
E7
RPC1
I/O
PU/–
B1
RPA1
I
PU
Receive Line Termination (RLT), port 1
PC(1:3).RPC(3:0) = 1000
b.
These input function controls together with LIM0.RTRS
the analog switch of the receive line interface: A logical
equivalence is build out of LIM0.RTRS and RLT.
D2
RPB1
I
PU
E7
RPC1
I
PU
B1
RPA1
I
PU
General Purpose Input (GPI), port 1
PC(1:3).RPC(3:0) = 1001
b.
The pin is set to input. The state of this input is reflected
in the register bits MFPI.RPA, MFPI.RPB or MFPI.RPC
respectively.
D2
RPB1
E7
RPC1
B1
RPA1
O
–
General Purpose Output High (GPOH), port 1
PC(1:3).RPC(3:0) = 1010
b.
The pin level is set fix to high level.
D2
RPB1
E7
RPC1
B1
RPA1
O
–
General Purpose Output Low (GPOL), port 1
PC(1:3).RPC(3:0) = 1011
b.
The pin level is set fix to low level.
D2
RPB1
E7
RPC1
B1
RPA1
O
–
Loss of Signal Indication Output (LOS), port 1
PC(1:3).RPC(3:0) = 1100
b.
The output reflects the Loss of Signal status as readable
in LSR0.LOS.
D2
RPB1
E7
RPC1
B1
RPA1
O
–
Receive Data Output Negative (RDON), port 1
PC(1:3).RPC(3:0) = 1110
b.
Receive data output negative for dual rail mode on
digital (framer) interface (LIM3.DRR = 1).
Bipolar violation output for single rail mode on digital
(framer) interface (LIM3.DRR = 0).
D2
RPB1
E7
RPC1
B1
RPA1
O
–
Receive Clock Output (RCLK), port 1
PC(1:3).RPC(3:0) = 1111
b. Default setting after reset
Receive clock output RCLK. After reset RCLK is
configured to be internally pulled up weekly. By setting
of PC5.CRP RCLK is an active output.
RCLK source and frequency selection is made by
CMR1.RS(1:0) if COMP = 1 or by CMR4.RS(2:0) if
COMP = 0.
D2
RPB1
E7
RPC1
Table 1
I/O Signals (cont’d)
Pin No. Ball
No.
Name
Pin Type Buffer
Type
Function