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參數(shù)資料
| 型號： | PEF22508E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, LBGA-256 |
| 文件頁數(shù)： | 171/193頁 |
| 文件大?。?/td> | 10683K |
| 代理商： | PEF22508E |
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Data Sheet
79
Rev. 1.0, 2005-06-02
OctalLIU
TM
PEF 22508 E
Functional Description
By the FCLKR input pin. In that case FCLKR input pin function must be selected by PC5.CSRP = 0 to use
the receiver clock from the framer.
In single rail mode of the transmit direction (LIM3.DRX = 0, LIM3), the input for the unipolar data of the framer is
XDIP.
If dual rail mode is selected in transmit direction by setting of register bit LIM3.DRX, the input for the positive rail
of the data is XDIP and the input for the negative rail of the data is the multi function port XDIN. Therefore one of
the both transmit multifunction ports must be configured to XDIN (for example PC1.XPX1(3:0) = 1101
B),
seeTable 29.
Clocking (sampling) of XDIP and XDIN is done with the rising or falling edge of the internal transmit clock, selected
by DIC3.RESX. The internal transmit clock can be sourced either
By the internal receive clock of the receive system (CMR2.IXSC = 1). To support the framer with these clock
FCLKR output pin function must be selected by PC5.CSRP = 1. or
By the FCLKX input pin (CMR2.IXSC = 0). In that case FCLKX is supported by the framer.
3.11
Test Functions
The following chapters describe the different test function of the OctalLIU
TM.
3.11.1
Pseudo-Random Binary Sequence Generation and Monitor
All bits of all slots in a E1T1/J1 frame are used for PRBS.
The OctalLIU
TM has the ability to generate and monitor pseudo-random binary sequences (PRBS). The generated
PRBS pattern is transmitted to the remote end on pins XL1/2 and can be inverted optionally. Generating and
monitoring of PRBS pattern is done according to ITU-T O.150 and ITU-T O.151.
The PRBS monitor senses the PRBS pattern in the incoming data stream. Synchronization is done on the inverted
and non-inverted PRBS pattern. The current synchronization status is reported in status and interrupt status
registers. Enabled by bit LCR1.EPRM each PRBS bit error increments an error counter BEC (BECL).
Synchronization is reached within 400 ms with a probability of 99.9% at a bit error rate of up to 10
-1.
The PRBS pattern (polynomials) can be selected to be 211-1, 215-1, 220-1or 223-1 by the register bits
TPC0.PRP(1:0) and LCR1.LLBP (LCR1), see Table 28. For definition of this polynomials see the Standards ITU-T
O.150, O.151. and TR62441. The polynomials 211-1 and 223-1 can be selected only if TPC0.PRM unequal 00
B.
Transmission of PRBS pattern is enabled by register bit LCR1.XPRBS. With the register bit LCR1.FLLB switching
between not inverted and inverted transmit pattern can be done.
The receive monitoring of PRBS patterns is enabled by register bit LCR1.EPRM. In general, depending on bit
LCR1.EPRM the source of the interrupt status bit ISR1.LLBSC changed, see register description. The type of
detected PRBS pattern in the receiver is shown in the status register bits PRBSSTA.PRS. Every change of the
bits PRS in PRBSSTA sets the interrupt bit ISR1.LLBSC if register bit LCR1.EPRM is set. No pattern is also
detected if the mode “alarm simulation” is active.
The detection of all_zero or all_ones pattern is done over 12, 16, 21 or 24 consecutive bits, depending on the
selected PRBS polynomial (211-1, 215-1, 220-1or 223-1 respectively). The detection of all_zero or all_ones is
independent on LCR1.FLLB.
The distinction between all-ones and all-zeros pattern is possible by combination of.
The information about the first reached PRBS status after the PRBS monitor was enabled (“PRBS pattern
detected” or “inverted PRBS pattern detected”) with
The status information “all-zero pattern detected” or “all-ones pattern detected”
If an “all-one” or an “all-zero” pattern is detected by the PRBS monitor, the interrupt status bit ISR1.LLBSC in E1
mode, or ISR3.LLBSC in T1/J1 mode respectively, is set not only once, but is set permanent.
Therefore, after reading of the interrupt status bit ISR1.LLBSC (E1 mode) or ISR3.LLBSC (T1/J1 mode), the
appropriate interrupt routine should set the interrupt mask bits IMR1.LLBSC (E1 mode) or IMR3.LLBSC (T1/J1
mode) to 1, after an “all-one” or an “all-zero” pattern was indicated, to avoid permanent interrupts issued by the
OctalLIU
TM. The PRBS status register bits PRBSSTA.PRS should be polled to detect changes in the pattern, for
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參數(shù)描述 |
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| PEF22508EV1.1-G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| PEF22508EV11G | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
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| PEF22508EV11GXT | 制造商:Lantiq 功能描述:LINE INTERFACE UNITS |
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