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| 型號： | pentium II cpu |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 23/84頁 |
| 文件大?。?/td> | 1092K |
| 代理商： | PENTIUM II CPU |
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Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
23
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Vcc
CORE
and Icc
CORE
supply the processor core and the TagRAM and BSRAM I/O buffers.
3. This specification applies only to the Pentium
II processor. Unless otherwise noted, this specification applies to all
Pentium II processor frequencies and cache sizes.
4. This specification applies only to the Pentium II processor when operating with a 100 MHz Pentium II processor system
bus. Unless otherwise noted, this specification applies to all Pentium II processor cache sizes.
5. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is
required. See
Section 2.5
and
Table 1
for more information.
6. Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation to the
processor.
7. V
CCL2
and I
CCL2
supply the second level cache. Unless otherwise noted, this specification applies to all Pentium II
processor cache sizes. Systems should be designed for these specifications, even if a smaller cache size is used.
8. V
TT
must be held to 1.5 V ±9%. It is recommended that V
TT
be held to 1.5 V ±3% while the Pentium II processor
system bus is idle. This is measured at the processor edge fingers.
9. These are the tolerance requirements, across a 20 MHz bandwidth, at the SC 242 connector pin on the bottom side of the
baseboard. The requirements at the SC 242 connector pins account for voltage drops (and impedance discontinuities)
across the connector, processor edge fingers, and to the processor core. Vcc
CORE
must return to within the static voltage
specification within 100
μ
s after a transient event.
10.These are the tolerance requirements, across a 20 MHz bandwidth, at the processor edge fingers. The requirements at
the processor edge fingers account for voltage drops (and impedance discontinuities) at the processor edge fingers and
to the processor core. Vcc
CORE
must return to within the static voltage specification within 2
μ
s after a transient event.
11.These are estimated values not actual measurements.
12.Max I
CC
measurements are measured at V
CC
max voltage, 95
°
C ±2
°
C, under maximum signal loading conditions. The
Max Icc currents specified do not occur simultaneously under the stress measurement condition.
13.Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage, at
maximum current output, is no greater than the nominal (i.e., typical) voltage level of Vcc
CORE
(Vcc
CORE_TYP
). In this
case, the maximum current level for the regulator, Icc
CORE_REG
, can be reduced from the specified maximum current
Icc
CORE _MAX
and is calculated by the equation:
Icc
CORE_REG
= Icc
CORE_MAX
×
Vcc
CORE_TYP
/ (Vcc
CORE_TYP
+ Vcc
CORE
Tolerance, Transient)
14.The current specified is the current required for a single Pentium II processor. A similar amount of current is drawn
through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is used (see
Section 2.1
).
15.The current specified is also for AutoHALT state.
16.Maximum values are specified by design/characterization at nominal Vcc
and nominal V
.
17.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum inductance
tolerable and reaction time of the voltage regulator. This parameter is not tested.
18.dI
CC
/dt specifications are measured and specified at the SC 242 connector pins.
19.V
CC5
and I
CC5
are not used by the Pentium II processors. This supply is used for the SC 242 Test Kit.
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