參數(shù)資料
型號： pentium II cpu
廠商： Intel Corp.
英文描述： Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器)
中文描述： 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器）
文件頁數(shù)： 32/84頁
文件大小： 1092K
代理商： PENTIUM II CPU
Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
32
Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
II processor frequencies and cache sizes.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.7 V at the processor edge fingers. All
TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the processor edge fingers.
3. Not 100% tested. Specified by design characterization.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 2.5 V +5%. See
Table 2
for pull-up resistor values.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These
timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
II processor frequencies and cache sizes.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 1.25 V at the processor core pins. All TAP
signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the processor core pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 2.5 V +5%. See
Table 2
for pull-up resistor values.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These
timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
Table 20. System Bus AC Specifications (TAP Connection)at the Processor Core Pins
1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T30: TCK Frequency
16.667
MHz
T31: TCK Period
60.0
ns
6
T32: TCK High Time
25.0
ns
6
@1.7 V
10
T33: TCK Low Time
25.0
ns
6
@0.7 V
10
T34: TCK Rise Time
5.0
ns
6
(0.7 V–1.7 V)
4, 10
T35: TCK Fall Time
5.0
ns
6
(1.7 V–0.7 V)
4, 10
T36: TRST# Pulse Width
40.0
ns
12
Asynchronous
10
T37: TDI, TMS Setup Time
5.0
ns
11
5
T38: TDI, TMS Hold Time
14.0
ns
11
5
T39: TDO Valid Delay
1.0
10.0
ns
11
6, 7
T40: TDO Float Delay
25.0
ns
11
6, 7, 10
T41: All Non-Test Outputs Valid Delay
2.0
25.0
ns
11
6, 8, 9
T42: All Non-Test Inputs Setup Time
25.0
ns
11
6, 8, 9, 10
T43: All Non-Test Inputs Setup Time
5.0
ns
11
5, 8, 9
T44: All Non-Test Inputs Hold Time
13.0
ns
11
5, 8, 9
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