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| 型號： | pentium II cpu |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 77/84頁 |
| 文件大?。?/td> | 1092K |
| 代理商： | PENTIUM II CPU |
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Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
77
DBSY#
I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on
the Pentium II processor system bus to indicate that the data bus is in use. The data bus is
released after DBSY# is deasserted. This signal must connect the appropriate pins on all
Pentium II processor system bus agents.
DEFER#
I
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the
addressed memory or I/O agent. This signal must connect the appropriate pins of all
Pentium II processor system bus agents.
DEP[7:0]#
I/O
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the
data bus. They are driven by the agent responsible for driving D[63:0]#, and must connect
the appropriate pins of all Pentium II processor system bus agents which use them. The
DEP[7:0]# signals are enabled or disabled for ECC protection during power on
configuration.
DRDY#
I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-cycle data transfer, DRDY# may be
deasserted to insert idle clocks. This signal must connect the appropriate pins of all Pentium
II processor system bus agents.
EMI
I
EMI pins should be connected to motherboard ground and/or to chassis ground through zero
ohm (0
) resistors. The zero ohm resistors should be placed in close proximity to the
Pentium II processor connector. The path to chassis ground should be short in length and
have a low impedance. These pins are used for EMI management purposes.
FERR#
O
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-
point error reporting.
FLUSH#
I
When the FLUSH# input signal is asserted, processors write back all data in the Modified
state from their internal caches and invalidate all internal cache lines. At the completion of
this operation, the processor issues a Flush Acknowledge transaction. The processor does
not cache any new data while the FLUSH# signal remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal following
an I/O write instruction, it must be valid along with the TRDY# assertion of the
corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH# to
determine its power-on configuration. See
P6 Family of Processors Hardware Developer’s
Manual
(Order Number 244001) for details.
HIT#
HITM#
I/O
I/O
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all Pentium II processor system
bus agents. Any such agent may assert both HIT# and HITM# together to indicate that it
requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
IERR#
O
The IERR# (Internal Error) signal is asserted by a processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the Pentium
II processor system bus. This transaction may optionally be converted to an external error
signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the
assertion of RESET#, BINIT#, or INIT#.
Table 41. Signal Description (Sheet 4 of 8)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium II processor | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
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