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| 型號： | pentium II cpu |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 75/84頁 |
| 文件大小： | 1092K |
| 代理商： | PENTIUM II CPU |
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Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
75
A20M#
I
If the A20M# (Address-20 Mask) input signal is asserted, the Pentium II processor masks
physical address bit 20 (A20#) before looking up a line in any internal cache and before
driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in
real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal following
an I/O write instruction, it must be valid along with the TRDY# assertion of the
corresponding I/O Write bus transaction.
During active RESET#, each processor begins sampling the A20M#, IGNNE#, and
LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency.
See
Table 9
. On the active-to-inactive transition of RESET#, each processor latches these
signals and freezes the frequency ratio internally. System logic must then release these
signals for normal operation.
ADS#
I/O
The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction
address on the A[35:3]# pins. All bus agents observe the ADS# activation to begin parity
checking, protocol checking, address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction. This signal must connect the appropriate
pins on all Pentium II processor system bus agents.
AERR#
I/O
The AERR# (Address Parity Error) signal is observed and driven by all Pentium II
processor system bus agents, and if used, must connect the appropriate pins on all Pentium
II processor system bus agents. AERR# observation is optionally enabled during power-on
configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent may
handle an assertion of AERR# as appropriate to the error handling architecture of the
system.
AP[1:0]#
I/O
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#,
A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers A[23:3]#. A
correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. This allows parity to be high when all the covered
signals are high. AP[1:0]# should connect the appropriate pins of all Pentium II processor
system bus agents.
BCLK
I
The BCLK (Bus Clock) signal determines the bus frequency. All Pentium II processor
system bus agents must receive this signal to drive their outputs and latch their inputs on the
BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
BERR#
I/O
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus
protocol violation. It may be driven by all Pentium II processor system bus agents, and must
connect the appropriate pins of all such agents, if used. However, Pentium II processors do
not observe assertions of the BERR# signal.
BERR# assertion conditions are configurable at a system level. Assertion options are
defined by the following options:
Enabled or disabled.
Asserted optionally for internal errors along with IERR#.
Asserted optionally by the request initiator of a bus transaction after it observes an
error.
Asserted by any bus agent when it observes an error in a bus transaction.
Table 41. Signal Description (Sheet 2 of 8)
Name
Type
Description
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