參數(shù)資料
型號： pentium II cpu
廠商： Intel Corp.
英文描述： Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器)
中文描述： 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器）
文件頁數(shù)： 26/84頁
文件大?。?/td> 1092K
代理商： PENTIUM II CPU
Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
26
Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
II processor frequencies and cache sizes.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.50 V at the processor edge fingers.
This reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to
receive the signal with a reference at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at
1.00 V at the processor edge fingers.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.7 V at the processor edge fingers.
This reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to
receive the signal with a reference at 1.25 V. All CMOS signal timings (compatibility signals, etc.) are referenced at
1.25 V at the processor edge fingers.
4. The internal core clock frequency is derived from the Pentium II processor system bus clock. The system bus clock to
core clock ratio is determined during initialization as described in
Section 2.5
.
Table 11
shows the supported ratios for
each processor.
5. The BCLK period allows a +0.5 ns -0.0ns tolerance for clock driver variation.
6. This specification applies to Pentium II processors when operating with a Pentium II processor system bus frequency of
100 MHz.
7. The BCLK offset time is the absolute difference needed between the BCLK signal arriving at the Pentium II processor
edge finger at 0.5 V vs. arriving at the core logic at 1.25 V. The positive offset is needed to account for the delay
between the SC 242 connector and processor core. The positive offset ensures both the processor core and the core logic
receive the BCLK edge concurrently.
8. See
Section 3.1
for Pentium II processor system bus clock signal quality specifications.
9. Not 100% tested. Specified by design characterization as a clock driver requirement.
Table 9.
System Bus AC Specifications (Clock) at the Processor Edge Fingers
1, 2, 3
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
System Bus Frequency
100.00
MHz
All processor core
frequencies
T1’: BCLK Period
10.0
ns
6
4, 5
T1B’: SC 242 to Core Logic BCLK Offset
0.78
ns
6
Absolute Value
7, 8
T2’: BCLK Period Stability
See
Table 10
T3’: BCLK High Time
2.1
ns
6
@>2.0 V
6
T4’: BCLK Low Time
1.97
ns
6
@<0.5 V
6
T5’: BCLK Rise Time
0.88
2.37
ns
6
(0.5 V–2.0 V)
6, 9
T6’: BCLK Fall Time
1.13
2.94
ns
6
(2.0 V–0.5 V)
6, 9
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