Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
41
3.3.1
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below V
SS
. The overshoot/undershoot guideline limits transitions beyond V
CC
or V
SS
due
to the fast signal edge rates. (See
Figure 16
for non-AGTL+ signals.) The processor can be
damaged by repeated overshoot events on 2.5 V tolerant buffers if the charge is large enough (i.e.,
if the overshoot is great enough). However, excessive ringback is the dominant detrimental system
timing effect resulting from overshoot/undershoot (i.e., violating the overshoot/undershoot
guideline will make satisfying the ringback specification difficult).
The overshoot/undershoot
guideline is 0.7 V
and assumes the absence of diodes on the input. These guidelines should be
verified in simulations
without the on-chip ESD protection diodes present
because the diodes
will begin clamping the 2.5 V tolerant signals beginning at approximately 0.7 V above the 2.5 V
supply and 0.7 V below V
SS
. If signals are not reaching the clamping voltage, this will not be an
issue. A system should not rely on the diodes for overshoot/undershoot protection as this will
negatively affect the life of the components and make meeting the ringback specification very
difficult.
3.3.2
Ringback Specification
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is
the voltage that the signal rings back to after achieving its maximum absolute
value
. (See
Figure 16
for an illustration of ringback.) Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL+ signals.
Ringback can be simulated with or without the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See
Table 25
for the signal ringback specifications for non-AGTL+ signals for simulations at the
processor core, and
Table 26
for guidelines on measuring ringback at the edge fingers.
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
II processor frequencies and cache sizes.
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
II processor frequencies and cache sizes.
Table 25. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Core
1
Input Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Non-AGTL+ Signals
0
→
1
1.7
V
16
Non-AGTL+ Signals
1
→
0
0.7
V
16
Table 26. Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement
1
Input Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Non-AGTL+ Signals
0
→
1
2.0
V
16
Non-AGTL+ Signals
1
→
0
0.7
V
16