參數(shù)資料
型號： pentium II cpu
廠商： Intel Corp.
英文描述： Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器)
中文描述： 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器）
文件頁數(shù)： 29/84頁
文件大?。?/td> 1092K
代理商： PENTIUM II CPU
Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
29
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
II processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.5 V at the processor edge fingers. All
CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. Valid delay timings for these signals are specified to 2.5 V +5%. See
Table 2
for pull-up resistor values.
6. To ensure recognition on a specific clock, the setup and hold times with respect to BCLK must be met.
7. INTR and NMI are only valid when the local APIC is disabled. LINT[1:0] are only valid when the local APIC is
enabled.
8. When driven inactive or after V
CC
CORE
, V
CCL2
, and BCLK become stable.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
II processor frequencies and cache sizes.
2. These specifications are tested during manufacturing.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core pins. All
CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. Valid delay timings for these signals are specified to 2.5 V +5%. See
Table 2
for pull-up resistor values.
6. This specification applies to Pentium II processors operating with a 100-MHz Pentium II processor system bus only.
7. To ensure recognition on a specific clock, the setup and hold times with respect to BCLK must be met.
8. INTR and NMI are only valid when the local APIC is disabled. LINT[1:0] are only valid when the local APIC is
enabled.
9. When driven inactive or after V
CC
CORE
, V
CCL2
, and BCLK become stable.
Table 14. System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers
1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
T11’: CMOS Output Valid Delay
1.00
10.5
ns
7
5
T12’: CMOS Input Setup Time
4.50
ns
8
6, 7, 8
T13’: CMOS Input Hold Time
1.50
ns
8
6, 7
T14’: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
7
Active and Inactive
states
T15’: PWRGOOD Inactive Pulse Width
10
BCLKs
7, 10
8
Table 15. System Bus AC Specifications (CMOS Signal Group)at the Processor Core Pins
1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
T11: CMOS Output Valid Delay
0.00
8.00
ns
7
5
T12: CMOS Input Setup Time
4.00
ns
8
6, 7, 8
T13: CMOS Input Hold Time
1.30
ns
8
6, 7
T14: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
7
Active and Inactive
states
T15: PWRGOOD Inactive Pulse Width
10
BCLKs
7, 10
9
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