- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369993 > pentium II processor (Intel Corp.) 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) PDF資料下載
參數(shù)資料
| 型號(hào)： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數(shù)： | 20/94頁 |
| 文件大?。?/td> | 892K |
| 代理商： | PENTIUM II PROCESSOR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
20
2.8.1.
ASYNCHRONOUS VS.
SYNCHRONOUS FOR SYSTEM BUS
SIGNALS
All GTL+ signals are synchronous to BCLK. All of the
CMOS, Clock, APIC and TAP signals can be applied
asynchronously to BCLK, except when running two
processors in FRC mode. Synchronization logic is
required on all signals going to both processors in
order to run in FRC mode.
Also note the timing requirements for FRC mode
operation. With FRC enabled, PICCLK must be of
BCLK and synchronized with respect to BCLK.
PICCLK must always lag BCLK as specified in
Table 15.
All APIC signals are synchronous to PICCLK. All
TAP signals are synchronous to TCK.
2.9.
Test Access Port (TAP)
Connection
Due to the voltage levels supported by other
components in the Test Access Port (TAP) logic, it is
recommended that the Pentium II processor be first
in the TAP chain and followed by any other
components within the system. A translation buffer
should be used to connect to the rest of the chain
unless one of the other components is capable of
accepting a 2.5 V input. Similar considerations must
be made for TCK, TMS and TRST#. Two copies of
each signal may be required with each driving a
different voltage level.
A Debug Port is described in the Pentium
II
Processor Developer’s Manual(Order Number
243341). The Debug Port will have to be placed at
the start and end of the TAP chain with the TDI of the
first component coming from the Debug Port and the
TDO from the last component going to the Debug
Port. In a 2-way MP system, be cautious when
including an empty Slot 1 connector in the scan
chain. All connectors in the scan chain must have a
processor installed to complete the chain or the
system must support a method to bypass empty
connectors; the Slot 1 terminator substrate connects
TDI to TDO. See the Pentium
II Processor
Developer’s Manual(Order Number 243341) for
more details.
2.10.
Maximum Ratings
Table 5 contains Pentium II processor stress ratings
only. Functional operation at the absolute maximum
and minimum is not implied nor guaranteed. The
processor should not receive a clock while subjected
to these conditions. Functional operating conditions
are given in the AC and DC tables. Extended
exposure to the maximum ratings may affect device
reliability. Furthermore, although the processor
contains protective circuitry to resist damage from
static electric discharge, one should always take
precautions to avoid high static voltages or electric
fields.
2.11.
Processor DC Specifications
The processor DC specifications in this section are
defined at the Pentium II processor edge fingers. See
Appendix A for the processor edge finger signal
definitions.
Most of the signals on the Pentium II processor
System Bus are in the GTL+ signal group. These
signals are specified to be terminated to 1.5 V. The
DC specifications for these signals are listed in
Table 8.
To allow connection with other devices, the Clock,
CMOS, APIC and TAP are designed to interface at
non-GTL+ levels. The DC specifications for these
pins are listed in Table 8.
Table 6 through Table 9 list the DC specifications for
the Pentium II processor. Specifications are valid
only
while
meeting
specifications
temperature, clock frequency and input voltages.
Care should be taken to read all notes associated
with each parameter.
for
case
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動(dòng)模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動(dòng)模塊處理器) |
| Pentium OverDrive Processor | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。