參數(shù)資料
型號(hào)： pentium II processor
廠商： Intel Corp.
英文描述： 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器)
中文描述： 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器）
文件頁數(shù)： 4/94頁
文件大小： 892K
代理商： PENTIUM II PROCESSOR
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
4
6.4. Thermal Specifications.................................81
6.4.1. BOXED PROCESSOR COOLING
REQUIREMENTS ................................81
7.0. ADVANCED FEATURES................................82
A.1 ALPHABETICAL SIGNALS REFERENCE....83
A.1.1 A[35:0]# (I/O).........................................83
A.1.2 A20M# (I)...............................................83
A.1.3 ADS# (I/O).............................................83
A.1.4 AERR# (I/O) ..........................................83
A.1.5 AP[1:0]# (I/O).........................................83
A.1.6 BCLK (I).................................................84
A.1.7 BERR# (I/O) ..........................................84
A.1.8 BINIT# (I/O) ...........................................84
A.1.9 BNR# (I/O).............................................84
A.1.10 BP[3:2]# (I/O).......................................84
A.1.11 BPM[1:0]# (I/O)....................................84
A.1.12 BPRI# (I)..............................................84
A.1.13 BR0# (I/O), BR1# (I)............................85
A.1.14 BSEL# (I/O) .........................................85
A.1.15 D[63:0]# (I/O).......................................85
A.1.16 DBSY# (I/O).........................................85
A.1.17 DEFER# (I)..........................................85
A.1.18 DEP[7:0]# (I/O)....................................85
A.1.19 DRDY# (I/O)........................................85
A.1.20 EMI.......................................................86
A.1.21 FERR# (O)...........................................86
A.1.22 FLUSH# (I)...........................................86
A.1.23 FRCERR (I/O) .....................................86
A.1.24 HIT# (I/O), HITM# (I/O)........................86
A.1.25 IERR# (O)............................................86
A.1.26 IGNNE# (I)...........................................87
A.1.27 INIT# (I)................................................87
A.1.28 LINT[1:0] (I)..........................................87
A.1.29 LOCK# (I/O).........................................87
A.1.30 PICCLK (I) ...........................................87
A.1.31 PICD[1:0] (I/O).....................................88
A.1.32 PM[1:0]# (O)........................................88
A.1.33 PRDY# (O) ..........................................88
A.1.34 PREQ# (I)............................................88
A.1.35 PWRGOOD (I).....................................88
A.1.36 REQ[4:0]# (I/O)....................................88
A.1.37 RESET# (I) ..........................................88
A.1.38 RP# (I/O)..............................................89
A.1.39 RS[2:0]# (I)...........................................89
A.1.40 RSP# (I)...............................................89
A.1.41 SLOTOCC# (O)...................................89
A.1.42 SLP# (I)................................................90
A.1.43 SMI# (I)................................................90
A.1.44 STPCLK# (I) ........................................90
A.1.454 TCK (I) ...............................................90
A.1.46 TDI (I)...................................................90
A.1.47 TDO (O)...............................................90
A.1.48 TESTHI (I)............................................90
A.1.49 THERMTRIP# (O) ...............................90
A.1.50 TMS (I).................................................90
A.1.51 TRDY# (I).............................................90
A.1.52 TRST# (I).............................................90
A.1.53 VID[4:0] (O)..........................................91
A.2 SIGNAL SUMMARIES.....................................91
FIGURES
Figure 1. Second Level (L2) Cache
Implementations....................................7
Figure 2. GTL+ Bus Topology...............................9
Figure 3. Stop Clock State Machine....................10
Figure 4. Timing Diagram of System Bus
Multiplier Signals.................................14
Figure 5. Example Schematic for System Bus
Multiplier Pin Sharing..........................15
Figure 6. BCLK to Core Logic Offset ..................32
Figure 7. BCLK, TCK, PICCLK Generic Clock
Wave Form .........................................32
Figure 8. System Bus Valid Delay Timings.........33
Figure 9. System Bus Setup and Hold Timings..33
Figure 10. FRC Mode BCLK to PICCLK Timing.34
Figure 11. System Bus Reset and Configuration
Timings ...............................................34
Figure 12. Power-On Reset and Configuration
Timings ...............................................35
Figure 13. Test Timings (TAP Connection).........36
Figure 14. Test Reset Timings............................36
Figure 15. BCLK, TCK, PICCLK Generic Clock
Wave form at the Processor Edge
Fingers................................................37
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