參數(shù)資料
型號(hào)： pentium II processor
廠商： Intel Corp.
英文描述： 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器)
中文描述： 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬(wàn)和333兆赫茲32位處理器）
文件頁(yè)數(shù)： 7/94頁(yè)
文件大?。?/td> 892K
代理商： PENTIUM II PROCESSOR
E
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
7
1.0.
INTRODUCTION
The Pentium
II processor is the next in the
Intel386, Intel486, Pentium and Pentium Pro
line of Intel processors. The Pentium II processor,
like the Pentium Pro processor, implements a
Dynamic Execution micro-architecture — a unique
combination of multiple branch prediction, data flow
analysis and speculative execution. This enables
the
Pentium II
processor
performance than the Pentium processor, while
maintaining binary compatibility with all previous
Intel architecture processors. The Pentium II
processor
also
executes
instructions for enhanced media and communication
performance. The Pentium II processor utilizes
multiple low-power states such as AutoHALT, Stop-
Grant, Sleep and Deep Sleep to conserve power
during idle times.
to
deliver
higher
MMX
technology
The Pentium II processor utilizes the same multi-
processing System Bus technology as the Pentium
Pro processor. This allows for a higher level of
performance for both uni-processor and two-way
multi-processor (2-way MP) systems. Memory is
cacheable for up to 512 MB of addressable memory
space, allowing significant headroom for business
desktop systems.
The Pentium II processor System Bus operates in
the same manner as the Pentium Pro processor
System Bus. The Pentium II processor System Bus
uses GTL+ signal technology. The Pentium II
processor deviates from the Pentium Pro processor
by using commercially available die for the L2
cache. The L2 cache (the TagRAM and burst
pipeline
memories) are now multiple die. Transfer rates
between the Pentium II processor core and the L2
cache are one-half the processor core clock
frequency and scale with the processor core
frequency. Both the TagRAM and BSRAM receive
clocked data directly from the Pentium II processor
core. As with the Pentium Pro processor, the L2
cache does not connect to the Pentium II processor
System Bus (see Figure 1). As with the Pentium Pro
processor, the Pentium II
dedicated L2 bus, thus maintaining the dual
independent bus architecture to deliver high bus
bandwidth and high performance (see Figure 1).
synchronous
static
RAM
(BSRAM)
processor
has
a
The Pentium II processor utilizes Single Edge
Contact (S.E.C.) cartridge packaging technology.
The S.E.C. cartridge allows the L2 cache to remain
tightly coupled to the processor, while enabling use
of high volume commercial SRAM components. The
L2 cache is performance optimized and tested at
the package level. The S.E.C. cartridge utilizes
surface mount technology and a substrate with an
edge finger connection. The S.E.C. cartridge
introduced on the Pentium II processor will also be
used in future Slot 1 processors.
The S.E.C. cartridge has the following features: a
thermal plate, a cover and a substrate with an edge
finger connection. The thermal plate allows
standardized heatsink attachment or customized
thermal solutions. The full enclosure also protects
the surface mount components. The edge finger
connection maintains socketability for system
configuration. The edge finger connector is noted as
‘Slot 1 connector’ in this and other documentation.
Pentium II Processor
Substrate and Components
Processor Core
Pentium
Pro Processor
Dual Die Cavity Package
Processor
Core
Tag
L2
L2
Schematic only
000756c
Figure 1. Second Level (L2) Cache Implementations
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